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Disabling SMIs on Intel(R) ICH5 chipsets

by Rajiv Ghosh-Roy

 

19 Feb 2008 (Updated 17 Dec 2009)

Avoid CPU overloads with xPC Target(TM) on Intel(R) chipsets by disabling SMIs

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Description

To successfully operate real-time software on any microprocessor system, control and management of all interrupt services is required. Unfortunately, depending on your BIOS, it may not be possible to turn off certain interrupts known as System Management Interrupts (SMIs). These interrupts are not accessible from operating system, kernel, or application software and the CPU cannot be instructed to ignore them. However, for some chipsets, such as the Intel ICH5 family, it is possible to programmatically prevent or disable the generation of SMIs.

Unexpected SMIs will cause random and spurious CPU overloads. The enclosed S-function and Simulink block will disable SMIs on the Intel ICH5 chipset family and help avoid these overloads.

Required Products xPC Target
MATLAB release MATLAB 7.5 (R2007b)
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Comments and Ratings (7)
28 Feb 2008 Ian Brown

My chipset is ICH7, and all I had to do to get this S-function to work was to add the correct PCIDevice IDs for ICH7. No more CPU Overload issues with xPC Target. (Although users of ICH7 should be aware that the ICH7 has an SMI_LOCK bit that can potentially be locked by the BIOS, which would prevent this function from working).

02 Jul 2008 Jing Huang

Great Job! Thanks a lot.

You may add one more item in the IntelChipSets table:
{0x27B8, "945GL"},

Also, please remove S from statement printf(S, "Intel chipset not found");

Thank you very much!

23 Oct 2008 Y Mehta  
25 Nov 2008 Ingo Tammer

Great job!

Your S-Function is also working for the Intel ICH9-Chipset (PCIDevice ID 0x2918)

Thank you very much!

11 Aug 2010 Ian

For ich10, can you please add:

{0x3A14, "ICH10D0"},
{0x3A16, "ICH10R"},
{0x3A18, "ICH10"},
{0x3A1A, "ICH10D"},

03 Dec 2010 Michael

This S-function worked for a Core 2 Duo (ICH7). I also have a Core i7 and a Xeon machine that both seem to be suffering from the same CPU Overload problems. I added the Device ID for the ISA Bridge (under PCI devices in xpcexplr) to the S-fuction code since that seemed to be what was done to add support for the other chipsets. For both the Xeon and Core i7, it seems to find the chipset, but gives me the following error: "Failed to Clear GBL_SMI_EN bit; SMI_LOCK may be set" Any suggestions?

10 May 2011 Chris

Added {0x2914, "ICH9D0"} and my SMI problems disappeared. The module also appears to prevent long TETs arising from enabled USB support (useful if one also uses the target machine for Windows and/or has a motherboard lacking PS/2 support).

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Updates
15 Oct 2008

Added more chipsets from the ICH7 family; updated to test the GBL_SMI_EN
bit if it got set. Please see the Readme_SMI.txt file for more details.

13 Jan 2009

Added chipsets for ICH9 based on user contributions, PCI IDs 0x2916 and 0x2918.

17 Dec 2009

Added PCI ID 0x2917.

Tag Activity for this File
Tag Applied By Date/Time
drivers Rajiv Ghosh-Roy 22 Oct 2008 09:49:35
real time Rajiv Ghosh-Roy 22 Oct 2008 09:49:35
xpc target Rajiv Ghosh-Roy 22 Oct 2008 09:49:35
cpuoverload Rajiv Ghosh-Roy 22 Oct 2008 09:49:35
smi Rajiv Ghosh-Roy 22 Oct 2008 09:49:35
cpuoverload Casey 26 Apr 2011 09:12:36

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