Disabling SMIs on Intel(R) ICH5 chipsets
by Rajiv Ghosh-Roy
19 Feb 2008
(Updated 17 Dec 2009)
Avoid CPU overloads with xPC Target(TM) on Intel(R) chipsets by disabling SMIs
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| File Information |
| Description |
To successfully operate real-time software on any microprocessor system, control and management of all interrupt services is required. Unfortunately, depending on your BIOS, it may not be possible to turn off certain interrupts known as System Management Interrupts (SMIs). These interrupts are not accessible from operating system, kernel, or application software and the CPU cannot be instructed to ignore them. However, for some chipsets, such as the Intel ICH5 family, it is possible to programmatically prevent or disable the generation of SMIs.
Unexpected SMIs will cause random and spurious CPU overloads. The enclosed S-function and Simulink block will disable SMIs on the Intel ICH5 chipset family and help avoid these overloads. |
| Required Products |
xPC Target
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| MATLAB release |
MATLAB 7.5 (R2007b)
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| Comments and Ratings (7) |
| 28 Feb 2008 |
Ian Brown
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| 02 Jul 2008 |
Jing Huang
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| 23 Oct 2008 |
Y Mehta
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| 25 Nov 2008 |
Ingo Tammer
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| 11 Aug 2010 |
Ian
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| 03 Dec 2010 |
Michael
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| 10 May 2011 |
Chris
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| Updates |
| 15 Oct 2008 |
Added more chipsets from the ICH7 family; updated to test the GBL_SMI_EN
bit if it got set. Please see the Readme_SMI.txt file for more details. |
| 13 Jan 2009 |
Added chipsets for ICH9 based on user contributions, PCI IDs 0x2916 and 0x2918. |
| 17 Dec 2009 |
Added PCI ID 0x2917. |
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