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Disabling SMIs on Intel(R) ICH5 chipsets

version 1.3.1 (6.9 KB) by

Avoid CPU overloads with xPC Target(TM) on Intel(R) chipsets by disabling SMIs

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To successfully operate real-time software on any microprocessor system, control and management of all interrupt services is required. Unfortunately, depending on your BIOS, it may not be possible to turn off certain interrupts known as System Management Interrupts (SMIs). These interrupts are not accessible from operating system, kernel, or application software and the CPU cannot be instructed to ignore them. However, for some chipsets, such as the Intel ICH5 family, it is possible to programmatically prevent or disable the generation of SMIs.
Unexpected SMIs will cause random and spurious CPU overloads. The enclosed S-function and Simulink block will disable SMIs on the Intel ICH5 chipset family and help avoid these overloads.

Comments and Ratings (11)


This is what I get:

Should I add only ISA Bridge?

Should I manually edit ich5.c file using Notepad?


Marco (view profile)

0x2810 for ICH8, ICH8R South Bridge.


Kosuke (view profile)

Jing Huang

Sometimes, users get an error message "Intel chipset not found" when using the disable SMI block. What you can do is to add the chipset of your target machine into the ich5.c. Here is how to do it.

1. Open the ich.5, find the IntelChipSets table, which looks like
IntelChipSets[] =
{0x2410, "82801AA_0"},
{0x2420, "82801AB_0"},
…… ……
The first field is the device ID, the second field is the name of the Southbridge chip. The name is not used by the code at all.

2. Find the device ID of the chipset in your target machine. Boot up the xpc target machine, on the Matlab command window, issue “xpctargetping, tg = xpc, getxpcpci(‘all’)”, you should see things like
>> getxpcpci('all')

List of installed PCI devices:

Intel *****
     Bus 0, Slot 0, IRQ 0
     Host Bridge
     VendorID 0x8086, DeviceID 0x29e0, SubVendorID 0x103c, SubDeviceID 0x1308
Intel *****
     Bus 0, Slot 31, IRQ 0
     ISA Bridge
     VendorID 0x8086, DeviceID 0x2916, SubVendorID 0x103c, SubDeviceID 0x1308
The ISA Bridge is what you want to add to the IntelChipSets table

3. Add the device ID into the IntelChipSets table. For the above example, add
{0x2916, “Whatever you name it”},
to the IntelChipSets table.

4. Issue “mex ich5.c” from matlab, and then rebuild your model.

Note: this change may not work on every chipset because the relevant registers might not at the same address.


Chris (view profile)

Added {0x2914, "ICH9D0"} and my SMI problems disappeared. The module also appears to prevent long TETs arising from enabled USB support (useful if one also uses the target machine for Windows and/or has a motherboard lacking PS/2 support).


This S-function worked for a Core 2 Duo (ICH7). I also have a Core i7 and a Xeon machine that both seem to be suffering from the same CPU Overload problems. I added the Device ID for the ISA Bridge (under PCI devices in xpcexplr) to the S-fuction code since that seemed to be what was done to add support for the other chipsets. For both the Xeon and Core i7, it seems to find the chipset, but gives me the following error: "Failed to Clear GBL_SMI_EN bit; SMI_LOCK may be set" Any suggestions?


Ian (view profile)

For ich10, can you please add:

{0x3A14, "ICH10D0"},
{0x3A16, "ICH10R"},
{0x3A18, "ICH10"},
{0x3A1A, "ICH10D"},

Ingo Tammer

Great job!

Your S-Function is also working for the Intel ICH9-Chipset (PCIDevice ID 0x2918)

Thank you very much!

Y Mehta

Jing Huang

Great Job! Thanks a lot.

You may add one more item in the IntelChipSets table:
{0x27B8, "945GL"},

Also, please remove S from statement printf(S, "Intel chipset not found");

Thank you very much!

Ian Brown

My chipset is ICH7, and all I had to do to get this S-function to work was to add the correct PCIDevice IDs for ICH7. No more CPU Overload issues with xPC Target. (Although users of ICH7 should be aware that the ICH7 has an SMI_LOCK bit that can potentially be locked by the BIOS, which would prevent this function from working).



Updated with more chipset ids.
You will need to mex the file ich5.c before using the block.

Updated license


Added PCI ID 0x2917.


Added chipsets for ICH9 based on user contributions, PCI IDs 0x2916 and 0x2918.

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