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BFSK design using system generator

by KONSTANTINOS VOSKAKIS

 

08 Jul 2008 (Updated 09 Jul 2008)

BFSK transmitter using System Generator 10.1

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Description

This is a thesis work and free to use. Please give some feedback.

Description of transmitter.

   The basic parts of the BFSK transmitter are the preamble and the data input circuit. The preamble sequence is positioned in front of each packet of 122 bits for a total of 128 bits packet. The main purpose of the preamble is to facilitate the reception, providing both bit and packet synchronization.
   The data input circuit mainly consists from memory elements and a convolutional encoder with r=1/2. Thus, the input bits must be stored in a temporary memory and be partitioned in blocks of 61 bits. Then the convolutional encoder doubles the bits and adds two more trail bits at the end of the message. A multiplexer makes sure that that the correct sequence, choosing between preamble and encoded bit, is propagating to the next stage.
   The next stage of the transmitter consists of two direct digital synthesizers (DDS), and a multiplexer that is fed with zeros and ones to choose between the two frequencies. For each bit, we allow 64 samples of the respective frequency to be transmitted. Although the implementation of the selection between the two frequencies is strait forward, the enable port of the multiplexer should be used along with a Matlab Code (MCode) block in order to prevent the propagation of some initial undefined states during initialization. The only functionality of the MCode block is to enable the multiplexer after the first bit of the preamble is detected.
   Finally, pulse shaping is not used and the addition of a single filter after the last multiplexer would suffice to implement this functionality.
   Receiver is available by email(kvoskaki@nps.edu) and is not 100% functional. Some advices are needed by anyone that could help.

Required Products Simulink
MATLAB release MATLAB 7.5 (R2007b)
Other requirements Xilinx's System Generator 10.1
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Comments and Ratings (2)
15 Sep 2008 Konstantinos Voskakis

The full design of transceiver is under way.

31 Dec 2008 yang lin

thank you!do you intering in ofdm

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Tag Activity for this File
Tag Applied By Date/Time
bfsk KONSTANTINOS VOSKAKIS 22 Oct 2008 10:09:28
system generator KONSTANTINOS VOSKAKIS 22 Oct 2008 10:09:28
xilinx KONSTANTINOS VOSKAKIS 22 Oct 2008 10:09:28
system generator Andres Marzo 27 Mar 2009 13:27:11
bfsk Nafees 11 May 2010 04:49:32
system generator Nafees 11 May 2010 04:49:39
xilinx Nafees 11 May 2010 04:49:46
bfsk boualem zouggari 18 May 2011 14:26:28
system generator boualem zouggari 18 May 2011 14:26:31

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