BFSK design using system generator

BFSK transceiver using SysGen 10.1

The transmitter is the combination of three distinct parts: the preamble, the data input and the modulation circuitry. The data is transmitted in blocks of 120 bits. An eight bit preamble with pattern 10101001 is attached in front of every packet to facilitate packet synchronization at the receiver. For simulation purposes, Simulink’s blocks ‘From Workspace’ and ‘To Workspace’ were used to supply the design with input bits and store them, respectively. The results were also visually verified at each stage using ‘Scope’ blocks.
Non-coherent BFSK. The choice of a Non-Coherent (NC) receiver design was made to eliminate any need for an extra circuit that would extract the phase information from the received signal. The receiver consists of the following subsystems: the two Correlators, the Decision Circuit, the Timing Circuit, the two Non-Coherent Matched Filters and the Decoding Subsystem. The Correlators and the Timing Circuit form the feedback path and the Non-Coherent Matched Filters and the Decoding Subsystem form the feed-forward path. The mixers are parts of both paths and are shown explicitly in the figure. The ‘Relational’ block compares the non-coherent matched filters’ outputs and decides the value of the received bit. The circuit designed closely matches the theoretical diagram found in any introductory textbook, with the addition of a time synchronization circuit and a Decode Subsystem.