ADC-DAC

SD Toolbox Reference

ADC-DAC

Models multi-bit ADC and DAC considering mismatch.

Library

SD Toolbox.

Description

The ADC-DAC block models multi-bit ADC and DAC considering mismatch.

This blocks determines automatically the threshold levels of the ADC and the output levels of the DAC based on the number of comparators desired in the quantizer (N_ADC). The number of DAC output levels is N_ADC + 1. The input range and the output range of the block are [-1, 1]. If a different range is required, gain blocks have to be placed in front and after the ADC-DAC block. For example, for achieving a range [-2, 2] a gain of 1/2 has to placed in front of the ADC-DAC block and a gain of 2 has to be placed after the ADC-DAC block. The ADC output of the block represents the digital output of the Sigma-Delta modulator, while the DAC output of the block is the feedback signal of the Sigma-Delta modulator.

It is well known that a mismatch among capacitors in the internal DAC of a multi-bit Sigma-Delta modulator causes an increase in the noise floor and in the harmonic distortion. Per-formance degradation is related to capacitor standard deviation (sigma), given by

where C_sp denotes the specific capacitance expressed in F/µm². Parameter A_C is expressed in µm, while parameter k in sqrt(F). Therefore, sigma is inversely proportional to the square root of the capacitor size (the constant k or A_C depends on the technology and is usually provided by the silicon foundry). If the value of k or A_C is not known, to enter the desired value of sigma, the following formula have to be used to determine the proper value of k

where C_TOT is the total capacitance of the DAC.

Considering that the sampling capacitor value impacts the constraints of almost all basic building blocks (e.g. operational amplifiers and voltage references) it has to be determined at the very beginning of the design phase. This makes approaches based on circuit simulator (e.g. Montecarlo simulation) ineffective (not only time consuming).

The ADC-DAC block can be used to evaluate if, given a sampling capacitor size, the performance degradation due to mismatch can be considered negligible with respect to thermal noise, or if some correction technique, such as dynamic element matching (DEM), has to be applied. The internal DAC is supposed to have an odd symmetry (as it happens in reality in all fully differential circuits and in all single ended circuits carefully designed), which means that the same elements are used to construct both positive and negative values. Under this assumption no even distortion can be introduced by DAC. This shrewdness is fundamental to avoid overrating mismatch effect on the output spectrum.

The mismatch information can be provided through parameter sigma or through a mismatch vector predetermined. The calculated values of the threshold levels of the ADC and the output levels of the DAC can be saved in a file.

Parameters

• Number of Comparators in Quantizers: Number of comparators to be used in the ADC (N_ADC)
• Consider Mismatch: Enables the modeling of the DAC capacitor mismatch
• Matching Parameter: Matching parameter provided by the silicon foundry k expressed in sqrt(F) (if Consider Mismatch is selected and Variance Vector Externally Provided is not selected)
• Total Capacitance: Total capacitance of the DAC in F, the unit capacitance is calculated as C_U = C_TOT/N_ADC (if Consider Mismatch is selected and Variance Vector Externally Provided is not selected)
• Variance Vector Externally Provided: Selects if the mismatch information is provided with an external input vector or with matching parameters
• Variance Vector: Vector with N_ADC elements containing matching information; variance has to be one and mean zero (if Consider Mismatch is selected and Variance Vector Externally Provided is selected)
• Enable LOG File: Enalbles saving the calculated values of the threshold levels of the ADC and the output levels of the DAC can be saved in a LOG file
• Name of LOG File (*.log): Name of the LOG file for saving the calculated values of the threshold levels of the ADC and the output levels of the DAC (if Enable LOG File is selected)

Power Spectral Density

Postprocessing