Generates a sine wave with sampling jitter (the derivative of the signal is analytically calculated).
Library
SD Toolbox.
Description
The Jittered Sine Wave block provides a sinusoid affected by sampling jitter.
The operation of a Switched Capacitor (SC) circuit depends on complete charge transfers during each of the clock phases. Once the analog signal has been sampled, the SC circuit is a sampled-data system where variations of the clock period have no direct effect on the circuit performance. Therefore, the effect of clock jitter on an SC circuit is completely described by computing its effect on the sampling of the input signal. This also means that the effect of clock jitter on a Sigma-Delta modulator is independent of the structure or order of the modulator. Clock jitter results in a non-uniform sampling time sequence, and produces an error which increases the total error power at the quantizer output. The magnitude of this error is a function of both the statistical properties of the jitter and the modulator input signal.
The error introduced when a sinusoidal signal x(t) with amplitude A and frequency fin is sampled at an instant, which is in error by an amount delta, is given by:
This effect can be simulated at behavioral level by adding this error to an ideal sine wave generator. The dericative dx(t)/dt is calculated analytically since x(t) is known.
Parameters
Amplitude: Amplitude of the sinusoidal signal in V
Bias: DC value of the sinusoidal signal in V
Frequency: Frequency of the sinusoidal signal in rad/s
Phase: Phase of the sinusoidal signal in rad
Sampling Jitter: RMS value of the sampling jitter in s (delta)
Sample Time: Period of the sampling signal in s (Ts = 1/fs, where fs is the sampling frequency)
Random Number Seed: Seed for the random number generator; different seeds among different blocks using the random number generator guarantee that the random sequences are uncorrelated