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Highlights from
INTERFACE BETWEEN MATLAB AND CADENCE FOR MACRO-MODEL EXTRACTION

• SIMECT.m
• SIMECT.m
• SIMECT.m
• SIMECT_PAR.m
• SIMECT_PAR.m
• SIMECT_PAR.m
• []=disp_AC(multi_in_out,model...
• gui_set_des_var(des_var)
• gui_simect_7(varargin)
• sys_funct_disp_mimo(varargin) SYS_FUNCT_DISP_MIMO M-file for sys_funct_disp_mimo.fig
• A_Fct =supzmax(A, fmax)
• [B_Trans_Fct A_Trans_Fct fr c...
• [B_Trans_Fct A_Trans_Fct]=ext...
• [B_norm A_norm]=norm_sfunct_d...
• [B_norm A_norm]=norm_sfunct_m...
• [R L C]=find_rlc(Rs,ZRAW,fr,e...
• [Vname Vval Iname Ival]=find_...
• []=convert_res_model(an_res,m...
• []=create_analog_model(subcel...
• []=disp_DC(model_par,dir_dc,c...
• []=gen_multiout_sim_model(sim...
• []=write_verilog_real(fid,nam... Write vhdl Constant vector from value and name
• []=write_verilog_vector(fid,n... Write vhdl Constant vector from value and name
• []=write_vhdl_real(fid,name,v... Write vhdl Constant vector from value and name
• []=write_vhdl_vector(fid,name... Write vhdl Constant vector from value and name
• [b,a]=invfreqs_local(g,w,vara... INVFREQS Analog filter least squares fit to frequency response data.
• [crt_meas,net_meas]=extract_n...
• [dir_dc inv_dc imp_dc]=extrac...
• [err err_mod err_phase]=fit_e...
• [fc phase_at_f0 Q]=find_fc(re...
• [good]=run_ocean(model_par, d...
• [idc out in idc_comm out_comm...
• [idc out1]=find_dc_par(sim_re...
• [ind,subckt_net_meas,netlist]...
• [line]=verilog_tr_decomp(namo...
• [line]=vhdl_tr_decomp(cdn_mod...
• [mod rep ]=get_ac_in(ac_an,or...
• [model rep ]=get_ac_out(ac_an...
• [multi_in_out model_in_out]=e...
• [res]=verilog_tr(sub_fct_str_... When a single element in vector
• [res]=vhdl_tr(sub_fct_str_idx... When a single element in vector
• [res]=vhdl_tr_smash(sub_fct_s...
• [simple_dc1,simple_dc2,simple...
• [syst_nm sub_syst_all_vect su... Open netlist
• addinfogene( model_par,trans_...
• cells_as_vector=extract_cells...
• decomp_write_tf_verilog(cdn_m... For verilog do not decompose
• decomp_write_tf_vhdl(cdn_mode... For SMASH do not decompose
• des_var=extract_des_var(net_r...
• disp_all_AC(model_par,multi_i...
• disp_all_DC(model_par,multi_i...
• disp_int_DC(model_par,sig,k,n...
• filepath_vhd=create_verilog_m...
• filepath_vhd=create_vhdl_mode...
• filepath_vhd=create_vhdl_mode...
• filname=convert_res_vhdl(vhdl...
• find_rlc_fc(rep_ac,imp_dc,num...
• find_trans(model_par, trans_a...
• indication=verif_extract_only...
• invIV( in )
• ls_estimate(xs,ys,out1,gn)
• model_in_out=get_gains(model_...
• model_in_out=get_model(model_...
• model_in_out=get_trf(model_pa...
• pathdef PATHDEF Search path defaults.
• plt_param( res, fig, dc_an, p...
• rep_trans=extract_tran(model_...
• set_check_off(numedit)
• set_check_on(numedit)
• set_edit_off(numedit)
• set_popup(popmenu,str,corrupt...
• set_popup_off(numpopup,str)
• set_popup_on(numpopup,str)
• simple_dc=get_dc(model_par,dc...
• solvev( vect )
• strcmpc(s1,s2)
• sub_fct_str=tf_decomp_real(Nu...
• sup_pzmax(B, A, fmax, rempole...
• tech=extract_tech(net_rep)
• valv( vect, pos )
• varres=extract_analp(varres, ...
• SIMECT_GUI.m
• extract_subckt_first_level.m
• gui_alloff.m
• gui_extract_off.m
• gui_fill_vars.m
• handpopmenu.m
• param_test_v_uni_v_uni_v1.m
• param_test_v_uni_v_uni_v1.m
• read_user_input.m
• simect_run.m
• simect_runpar.m
• update_model.m
• var_test_i_diff_i_diff_v1.m
• var_test_i_uni_v_diff_v1.m
• var_test_v_diff_i_uni_v1.m
• var_test_v_uni_v_uni_v1.m
• var_test_v_uni_v_uni_v1.m
• verif_par.m
• write_variant_to_file.m
• write_variant_to_gui.m
• CCCS_lin_in_comm_out_comm
• CCCS_lin_in_comm_out_diff
• CCCS_lin_in_diff_out_comm
• CCCS_lin_in_diff_out_diff
• CCVS_lin_in_comm_out_comm
• CCVS_lin_in_comm_out_diff
• CCVS_lin_in_diff_out_comm
• CCVS_lin_in_diff_out_diff
• VCCS_lin_in_comm_out_comm
• VCCS_lin_in_comm_out_diff
• VCCS_lin_in_diff_out_comm
• VCCS_lin_in_diff_out_diff
• VCVS_lin_in_comm_out_comm
• VCVS_lin_in_comm_out_diff
• VCVS_lin_in_diff_out_comm
• VCVS_lin_in_diff_out_diff_new
• View all files