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Code covered by the BSD License

xilinxbram(filename, dataary,... XILINXBRAM Generate 18 kbit BRAM contents for Xilinx FPGA (Spartan, Virtex).
xilinxbraminit XILINXBRAMINIT Initialize 18 kbit BRAM contents for Xilinx FPGA.
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XILINXBRAM - Xilinx FPGA Block RAM Init

12 Feb 2010

Matlab code for Xilinx FPGA (Spartan, Virtex) 18k block RAM declaration using VHDL or Verilog

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Description	Use xilinxbram.m and xilinxbraminit.m functions to generate VHDL or Verilog fraction of code to initialize Xilinx FPGA (Spartan, Virtex) 18k block RAM. Recent revision is also available here: http://radio.feld.cvut.cz/personal/matejka/wiki/doku.php?id=root:en:projects
MATLAB release	MATLAB 7 (R14)

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Everyone's Tags	block ram, data export, verilog, vhdl, xilinx
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