qpsk_sl_cntl

function c = qpsk_sl_cntl

% 

c = hdlnewcontrol(mfilename);

c.generateHDLFor('qpsk_sl/QPSK Modulator for HDL');

c.set( ...
	'AddInputRegister',            'on',...
	'AddOutputRegister',           'on',...
	'AddPipelineRegisters',        'off',...
	'BlockGenerateLabel',          '_gen',...
	'CastBeforeSum',               'on',...
	'CheckHDL',                    'off',...
	'ClockEnableInputPort',        'clk_enable',...
	'ClockEnableOutputPort',       'ce_out',...
	'ClockHighTime',               5,...
	'ClockInputPort',              'clk',...
	'ClockInputs',                 'Single',...
	'ClockLowTime',                5,...
	'ClockProcessPostfix',         '_process',...
	'CodeGenerationOutput',        'GenerateHDLCode',...
	'CoeffMultipliers',            'Multiplier',...
	'CoeffPrefix',                 'coeff',...
	'CoefficientSource',           'Internal',...
	'ComplexImagPostfix',          '_im',...
	'ComplexRealPostfix',          '_re',...
	'DALUTPartition',              -1,...
	'DARadix',                     2,...
	'EDAScriptGeneration',         'on',...
	'EnablePrefix',                'enb',...
	'EntityConflictPostfix',       '_block',...
	'ErrorMargin',                 4,...
	'FIRAdderStyle',               'linear',...
	'ForceClock',                  'on',...
	'ForceClockEnable',            'on',...
	'ForceReset',                  'on',...
	'FracDelayPort',               'filter_fd',...
	'GainMultipliers',             'Multiplier',...
	'GenerateCoSimBlock',          'off',...
	'GeneratedModelName',          '',...
	'GeneratedModelNamePrefix',    'gm_',...
	'HDLCompileFilePostfix',       '_compile.do',...
	'HDLCompileInit',              'vlib work\n',...
	'HDLCompileTerm',              '',...
	'HDLCompileVHDLCmd',           'vcom %s %s\n',...
	'HDLCompileVerilogCmd',        'vlog %s %s\n',...
	'HDLControlFiles',             {},...
	'HDLMapFilePostfix',           '_map.txt',...
	'HDLMapSeparator',             '',...
	'HDLSimCmd',                   'vsim -novopt work.%s\n',...
	'HDLSimFilePostfix',           '_sim.do',...
	'HDLSimInit',                  'onbreak resume\nonerror resume\n',...
	'HDLSimTerm',                  'run -all\n',...
	'HDLSimViewWaveCmd',           'add wave sim:%s\n',...
	'HDLSynthCmd',                 'add_file %s\n',...
	'HDLSynthFilePostfix',         '_synplify.tcl',...
	'HDLSynthInit',                'project -new %s.prj\n',...
	'HDLSynthTerm',                'set_option -technology VIRTEX4\nset_option -part XC4VSX35\nset_option -synthesis_onoff_pragma 0\nset_option -frequency auto\nproject -run synthesis\n',...
	'HighlightAncestors',          'on',...
	'HighlightColor',              'cyan',...
	'HoldInputDataBetweenSamples', 'on',...
	'HoldTime',                    2,...
	'IgnoreDataChecking',          0,...
	'InitializeTestBenchInputs',   'off',...
	'InlineConfigurations',        'on',...
	'InputPort',                   'filter_in',...
	'InputType',                   'std_logic_vector',...
	'InstanceGenerateLabel',       '_gen',...
	'InstancePrefix',              'u_',...
	'LoopUnrolling',               'off',...
	'MultifileTestBench',          'off',...
	'Name',                        'filter',...
	'OptimizeForHDL',              'off',...
	'OptimizeTimingController',    'on',...
	'OutputGenerateLabel',         'outputgen',...
	'OutputPort',                  'filter_out',...
	'OutputType',                  'Same as input type',...
	'PackagePostfix',              '_pkg',...
	'PipelinePostfix',             '_pipe',...
	'ProductOfElementsStyle',      'linear',...
	'ReservedWordPostfix',         '_rsvd',...
	'ResetAssertedLevel',          'Active-high',...
	'ResetInputPort',              'reset',...
	'ResetLength',                 2,...
	'ResetType',                   'Asynchronous',...
	'ReuseAccum',                  'off',...
	'SafeZeroConcat',              'on',...
	'ScaleWarnBits',               3,...
	'SerialPartition',             -1,...
	'SimulatorFlags',              '',...
	'SplitArchFilePostfix',        '_arch',...
	'SplitEntityArch',             'off',...
	'SplitEntityFilePostfix',      '_entity',...
	'SumOfElementsStyle',          'linear',...
	'SynthesisOffDirective',       '',...
	'SynthesisOnDirective',        '',...
	'TargetDirectory',             'auto_hdlsrc_qpsk',...
	'TargetLanguage',              'VHDL',...
	'TestBenchClockEnableDelay',   1,...
	'TestBenchCoeffStimulus',      [],...
	'TestBenchDataPostfix',        '_data',...
	'TestBenchFracDelayStimulus',  [],...
	'TestBenchPostfix',            '_tb',...
	'TestBenchReferencePostFix',   '_ref',...
	'TestBenchStimulus',           [],...
	'TestBenchUserStimulus',       [],...
	'UseAggregatesForConst',       'off',...
	'UseDotLayout',                'off',...
	'UseRisingEdge',               'off',...
	'UseSLAutoRoute',              'on',...
	'UseVerilogTimescale',         'on',...
	'UserComment',                 'Modeling by Akemi Tanaka of CYBERNET SYSTEMS',...
	'VHDLFileExtension',           '.vhd',...
	'VectorPrefix',                'vector_of_',...
	'Verbosity',                   1,...
	'VerilogFileExtension',        '.v');