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HDL Verifier Support Package for Xilinx FPGA Boards

Use FPGA-in-the-loop (FIL) verification on Xilinx FPGA boards.

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HDL Verifier™ Support Package for Xilinx® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier and supported Xilinx hardware. With FIL simulation, use MATLAB® or Simulink® to test designs in real hardware for any existing HDL code. The HDL code can either be manually written or generated from a model subsystem.

This support package is functional for R2013a and beyond.

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Tao Jia

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MATLAB 8.1 (R2013a)

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