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MATLAB/Xilinx ISIM Link

MATLAB/Xilinx ISIM Link

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RTL Module Behavioral Simulation using Xilinx ISIM within MATLAB Environment

runverilogmodule(...
function opVecCell = runverilogmodule(...
    module_folder_path, module_tb_name, ...
    ipSetCell, opSetCell, ...
    ipVecCell, use_debug_opt)
%RUNVERILOGMODULE run verilog module using input test vectors
%prepare inputs
% 1- read each input vector
% 2- convert it to hex words using the fixed point formats in the ipSetCell
% 3- write inputs to files using names in ipSetCell

%IP/OP
% - ipSetCell/opSetCell: input/output settings in the cell form as follow:
% {module name, fixed point format}.. eg. , {'opSig_80MHz_vector','s2.9';
% 'opSig_2','u3.1'}
%
% - ipVecCell/ipVecCell: input/output vectors. each cell row contains one
% signal/vector with settings specified in the same raw index of
% ipSetCell/opSet/Cell.... eg.: ipVecCell = {[ipSig1]; [ipSig2];..}

%By: Mohamed Abdelsalam
%Date: 25 June 2013

if(strcmp(module_folder_path(end),'\')==0)
    module_folder_path = [module_folder_path '\'];
end

%Check if a valid module exe exists (and updated)
need_make = 0;
%date/time info vector (check if any of the required files is outdated)
f_info = dir([module_folder_path module_tb_name '.exe']);
if(isempty(f_info))
    need_make = 1;
else
    date_exe_vec = datevec({f_info.date});
    f_info = dir([module_folder_path module_tb_name '.prj']);
    date_info_vec = datevec({f_info.date});
    f_info = dir([module_folder_path '*.v']);
    date_info_vec = [date_info_vec; datevec({f_info.date})];

    abs_date_in_sec = date_info_vec * ...
        [365*24*60*60; 30*24*60*60; 24*60*60; 60*60; 60; 1];
    abs_date_exe_in_sec = date_exe_vec * ...
        [365*24*60*60; 30*24*60*60; 24*60*60; 60*60; 60; 1];

    if(any(abs_date_in_sec > abs_date_exe_in_sec))
        need_make = 1;
    end
end

if(need_make)
    %use fuse command in dos to generate ISIM exe file
    %By: Mohamed A. Ali
    %Date: 25 June 2013

    %search for <module_tb_name>.prj file.. if not exist, create it and
    %list all modules (*.v) in it.
    %Note: The project file (PRJ) is used with the fuse command to provide
    %a list of all the files associated with a design. The PRJ file
    %contains the  language, library name and the design file.

    if(strcmp(getenv('XILINX_ISE_DS'),''))
        reply = input(['Please enter the path of Xilinx ISE_DS folder', ...
            '(environment variable XILINX_ISE_DS will be created for', ...
            'this path. e.g. C:\\Xilinx\\14.5\\ISE_DS)'],'s');
        if(strcmp(reply(end),'\')||strcmp(reply(end),'/'))
            reply = reply(1:end-1);
        end
        system(['setx XILINX_ISE_DS ' reply]);
    end

    Xilinx_fuse_command_path = '%XILINX_ISE_DS%\ISE\bin\nt\fuse';

    s = system(['dir ' module_folder_path module_tb_name '.prj']);
    if s == 1 %module_tb_name.prj does not exist
        %list all .v modules
        f = dir([module_folder_path '*.v']);
        n = size(f,1);
        str = [];
        for i = 1:n
            str = [str, 'Verilog work ', f(i).name, ' \n'];
        end
        str = sprintf(str);


        %create module_tb_name.prj file
        prj_fid = fopen([module_folder_path module_tb_name '.prj'],'w');
        fwrite(prj_fid,str);
        fclose(prj_fid);
    end

    fuse_settings = ...
        ' -intstyle ise -incremental ';
    fuse_lib =...
        ' -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o ';
    make_command = [Xilinx_fuse_command_path, fuse_settings, fuse_lib, ...
        module_folder_path, module_tb_name, '.exe ', ...
        '-prj ', module_folder_path, module_tb_name, '.prj',...
        ' work.', module_tb_name];
    dos(make_command);
end

%RUN_V_MODULE run verilog module simulation model(testbench ISIM exe)
%By: Mohamed A. Ali
%Date: 25 June 2013

Xilinx_folder_path = getenv('XILINX_ISE_DS');
idx = findstr(Xilinx_folder_path,'ISE_DS');
Xilinx_folder_path = Xilinx_folder_path(1:idx-1);

n_ip = size(ipVecCell,1);
if n_ip ~= size(ipSetCell,1)
    error('');
end

%read the input into files (used internally by the module testbench)
for ip_idx = 1: n_ip
    ip_fp_format =  ipSetCell{ip_idx,2};
    ip_vec = ipVecCell{ip_idx,1};
    isSigned = (lower(ip_fp_format(1)) == 's');
    dot_idx = find(ip_fp_format == '.');
    n_int_bits = str2double(ip_fp_format(2:dot_idx-1));
    n_frac_bits = str2double(ip_fp_format(dot_idx+1:end));
    ip_vec = fix(ip_vec*2^n_frac_bits);
    if isSigned
        ip_vec = min(...
            max(ip_vec,-2^(n_int_bits+n_frac_bits)),...
            2^(n_int_bits+n_frac_bits)-1);
    else
        ip_vec = min(...
            max(ip_vec*2^n_frac_bits,0),...
            2^(n_int_bits+n_frac_bits)-1);
    end
    ip_vec(ip_vec < 0) = 2^(n_int_bits + n_frac_bits)+ip_vec(ip_vec < 0);
    ip_vec_hex = dec2hex(ip_vec);
    file_name =  ipSetCell{ip_idx,1};
    dlmwrite([file_name '.txt'],ip_vec_hex,'delimiter','','newline', 'pc');
end

%create op files to be used internally by the module testbench
n_op = size(opSetCell,1);
for op_idx = 1:n_op
    file_name =  opSetCell{op_idx,1};

    fid = fopen([file_name '.txt'],'w');
    fclose(fid);
end

%run module
run_xilinx_cmd = ['%SystemRoot%\system32\cmd.exe /c ' ...
    Xilinx_folder_path 'ISE_DS\settings64.bat '];

%tcl batch
tcl_fid = fopen([module_folder_path 'isim.cmd'],'w');
if use_debug_opt
    fwrite(tcl_fid,'run 1 ns');
    run_opt = ' -gui'; %' -gui' --> ISIM GUI debugging
else
    fwrite(tcl_fid,'run all; exits;');
    run_opt = ''; %'' --> for no debugging
end

fclose(tcl_fid);


tun_tcl_cmd = [' -tclbatch ' module_folder_path 'isim.cmd'];

dos([run_xilinx_cmd module_folder_path module_tb_name run_opt tun_tcl_cmd ]);

%read module op into the opVecCell
opVecCell = cell(n_op,1);
for op_idx = 1:n_op
    file_name =  opSetCell{op_idx,1};
    %file_name = [module_folder_path file_name '.txt'];

    op_vec_hex = [];
    while(isempty(op_vec_hex)||~any(strcmp(op_vec_hex,'end') == 1))
        fid = fopen([file_name '.txt'] ,'r');
        op_vec_hex  = textscan(fid,'%s');
        op_vec_hex = op_vec_hex{:};
        fclose(fid);
    end

    op_fp_format =  opSetCell{op_idx,2};
    isSigned = (lower(op_fp_format(1)) == 's');
    dot_idx = find(op_fp_format == '.');
    n_int_bits = str2double(op_fp_format(2:dot_idx-1));
    n_frac_bits = str2double(op_fp_format(dot_idx+1:end));

    op_vec = [];
    for cnt = 1:size(op_vec_hex,1)-1
        if(isempty(findstr(op_vec_hex{cnt,1},'x')))
            op_vec = [op_vec; op_vec_hex{cnt,1}];
        end
    end
    op_vec = hex2dec(op_vec);

    if isSigned
        op_vec_neg = op_vec(op_vec >= 2^(n_int_bits + n_frac_bits -1));
        op_vec_neg = -(2^(n_int_bits + n_frac_bits)-op_vec_neg);
        op_vec(op_vec >= 2^(n_int_bits + n_frac_bits -1)) = op_vec_neg;
    end
    op_vec = op_vec / 2^n_frac_bits;
    opVecCell{op_idx,1} = op_vec;
end

for op_idx = 1:n_op
    file_name =  opSetCell{op_idx,1};
    delete([file_name '.txt']);
end

for ip_idx = 1:n_ip
    file_name =  ipSetCell{ip_idx,1};
    delete([file_name '.txt']);
end

%delete other intermediate files
if exist('fuse.log','var')
    delete('fuse.log');
end
if exist('fuse.xmsgs')
    delete('fuse.xmsgs');
end
if exist('fuseRelaunch.cmd')
    delete('fuseRelaunch.cmd');
end
if exist('isim.wdb')
    delete('isim.wdb');
end

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