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MATLAB/Xilinx ISIM Link

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RTL Module Behavioral Simulation using Xilinx ISIM within MATLAB Environment

sc(ipSig)
function opSig = sc(ipSig)
debug_mode = false;
ipVecs = {ipSig};
ipSettings = {'ipSig', 's2.9'};
opSettings = {'opSig', 's2.9'};
opVecs = runverilogmodule([cd '\SC_module'],...
    'sc_tb', ipSettings, opSettings, ipVecs, debug_mode);
opSig = opVecs{1};
opSig = opSig(2:end); %compensate module delay

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