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Model-Based Design and FPGA Implementation with Simulink

09 Jan 2006 (Updated 16 Jan 2006)

No BSD License

We introduce Simulink® for Model-Based Design in the context of FPGA implementation and verificatio

File Information
Description	Using Simulink for Model-Based Design can shorten the design cycle of embedded systems and hardware products. By offering a unified environment to explore design tradeoffs, and eventually to implement and verify a design on target hardware, including GPPs, DSPs, and FPGAs, you will be able to design in weeks what normally takes months. You can find a link a webinar that describes this application at the following link, http://www.mathworks.com/cmspro/req11162.html?eventid=31217
Required Products	Fixed-Point Toolbox EDA Simulator Link MQ Signal Processing Blockset Signal Processing Toolbox Simulink Simulink Fixed Point Video and Image Processing Blockset
MATLAB release	MATLAB 7.0.4 (R14SP2)
Other requirements	Xilinx System Generator, Altera DSP builder, ModelSim
Zip File Content
Other Files	Model Based Design and the FPGA Implementation in Simulink/edgecmds.m, Model Based Design and the FPGA Implementation in Simulink/edgecmds_v.m, Model Based Design and the FPGA Implementation in Simulink/edge_detection_design2.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_es.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_fixed.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_fixed_elaborate.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_fixed_elaborate_Altera.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_fixed_elaborate_Altera_HIL.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_fixed_elaborate_lms.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_fixed_elaborate_lms_v.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_fixed_elaborate_xilinx.mdl, Model Based Design and the FPGA Implementation in Simulink/edge_detection_menu.m, Model Based Design and the FPGA Implementation in Simulink/example_sel.txt, Model Based Design and the FPGA Implementation in Simulink/filter_altera.mdl, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/filter2d.vhd, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/filter2d_compile.do, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/filter2d_map.txt, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/filter2d_pkg.vhd, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/filter2d_synplify.tcl, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/transcript, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/vsim.wlf, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/work/filter2d/rtl.asm, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/work/filter2d/rtl.dat, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/work/filter2d/_primary.dat, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/work/filter2d_pkg/body.asm, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/work/filter2d_pkg/body.dat, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/work/filter2d_pkg/_primary.dat, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/work/filter2d_pkg/_vhdl.asm, Model Based Design and the FPGA Implementation in Simulink/hdlsrc/work/_info, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/filter2d_v.v, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/filter2d_v_wrap.vhd, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/vsim.wlf, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/work/filter2d_v/verilog.asm, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/work/filter2d_v/_primary.dat, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/work/filter2d_v/_primary.vhd, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/work/filter2d_v_wrap/rtl.asm, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/work/filter2d_v_wrap/rtl.dat, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/work/filter2d_v_wrap/_primary.dat, Model Based Design and the FPGA Implementation in Simulink/hdlsrc_v/work/_info, Model Based Design and the FPGA Implementation in Simulink/sattelite.gif, Model Based Design and the FPGA Implementation in Simulink/transcript

Tags for This File
Everyone's Tags	altera, fpga(3), hardware targets, modelsim, verilog, vhdl(2), xilinx(2)
Tags I've Applied
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Comments and Ratings (7)
13 Jan 2006	T K	The link to the zip file does not work!
12 Feb 2006	Jagdeep Singh	Excellent work done! Its been really helpful
20 Apr 2006	mike lee
28 Apr 2006	andi yusuf	IS GOOD ... HELP ME FOR FPGA PROBLEM
30 Jan 2007	karthik rajendra	hello i have a problem.i wanted to know whether we can write code for delta sigma adc using matlab and vhdl in fpga. please help me if u have the code.
07 May 2008	park jusang
08 Jun 2009	Srinivasulu Narasepalli

Please login to add a comment or rating.

Updates
16 Jan 2006	Chnaged the required products and added alink to the webinar
16 Jan 2006	Chnaged the required products and added alink to the webinar
16 Jan 2006	Added a link to the webinar and the requirments

Tag Activity for this File
Tag	Applied By	Date/Time
hardware targets	Ali Behboodian	22 Oct 2008 08:11:58
fpga	Ali Behboodian	22 Oct 2008 08:11:58
vhdl	Ali Behboodian	22 Oct 2008 08:11:58
verilog	Ali Behboodian	22 Oct 2008 08:11:58
modelsim	Ali Behboodian	22 Oct 2008 08:11:58
altera	Ali Behboodian	22 Oct 2008 08:11:58
xilinx	Ali Behboodian	22 Oct 2008 08:11:58
vhdl	Kaleshwari Swarna	01 Feb 2009 06:22:39
fpga	Peter Baas	21 Jul 2009 04:33:08
xilinx	amit gupta	01 Oct 2009 16:29:32
fpga	amit gupta	01 Oct 2009 16:29:36

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