image thumbnail

Model-Based Design and FPGA Implementation with Simulink

by

 

09 Jan 2006 (Updated )

We introduce SimulinkĀ® for Model-Based Design in the context of FPGA implementation and verificatio

edgecmds_v
function tclcmd = edgecmds_v
% HDLFILTERLINKCMDS - Creates Tcl cmds for Inverter Model
%   The returned cell array can be passed as parameters ('cmd') to
%   VSIMULINK.  This will start ModelSim and compile the HDL.
%   Also, the model will be loaded for cosimulation with 
%   inverter.MDL
%
% See also VSIMULINK


tmpdir = fullfile(pwd, 'hdlsrc_v');

% TCL for ModelSim
unixprojdir  = strrep(tmpdir,'\','/'); % ModelSim prefers Unix style pathnames
unixprojdir  = strrep(unixprojdir, ' ', '\ '); % backslash spaces
tclcmd = { ['cd ',unixprojdir],...            
           'vlib work',... %create library (if necessary)
           'vlog filter2d_v.v',...             
           'vsim work.filter2d_v',...           
           'wrapverilog -nocompile filter2d_v',...    
           'vcom filter2d_v_wrap.vhd',...     
           'vsimulink work.filter2d_v_wrap',...      
           'add wave -height 100 -radix decimal -format analog-step -scale 0.3 -offset 0 sim:/filter2d_v_wrap/filter_in',...
           'add wave -height 100 -radix decimal -format analog-step -scale 0.3 -offset 0 sim:/filter2d_v_wrap/filter_out',...
           'add wave -height 100 -radix decimal -format analog-step -scale 0.3 -offset 0 sim:/filter2d_v_wrap/CLK',...
           'add wave -height 100 -radix decimal -format analog-step -scale 0.3 -offset 0 sim:/filter2d_v_wrap/reset',...
           'catch { wm geometry $vsimPriv(WaveWindows) 521x600+10+10 }',...
         };

% [EOF]

Contact us