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updated 22 days ago

HDL Coder™ Support Package for Altera® SoC by MathWorks HDL Coder Team

Use Simulink and HDL Coder to configure programmable logic on Altera Cyclone V SoCs (fpga, soc)

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updated 1 month ago

Recalculate rectification indices for rectangle image by Peter Seibold

For fast image processing this script extracts parameters for stereo image rectification. (image processing, stereo vision, calibration)

Double_versus_uint

FindLargestRectanglesPUS(I, crit, minSize)

extractIndicesForStereoPair

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updated 6 months ago

fft_split.m Split the FFT of two real sequences by Patrick Fleischmann

splits the FFT of a sequence x=x1+i*x2 into the FFTs of the real input sequences x1,x2 (signal processing, fft, embedded code)

fft_split(X)

fft_split_tb.m

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updated almost 3 years ago

Bit-slicing function for integer matrices by Damon Bradley

function E = bitreslice(A,b_old, b_new, echo_on) Re-packages bits of a matrix of integers. (bit vector, bit slicing, rearrange bits)

bitreslice(A,b_old, b_new, echo_on)

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updated 3 years ago

GPS Receiver using Xilinx FPGA and TI DSP by Dick Benson

These model files move from a system level GPS receiver channel to actual operating hardware. (gps, tracking, timing)

ca=ca_fpga;

example_sel2html(fn,new)

GPS_Capture.m

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updated 3 years ago

IEEE single precision floating point number <=> uint 32 converter by Igal

C based S-Function blocks implementing biderectional convertion single precision floats <=> uint32 (fpga, floating point core, ieee single)

ieee_float_2_uint32_and_back

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updated almost 4 years ago

EZ Video Component Builder for Altera Avalon Streaming by Atsushi Matsumoto

Sample models to create Altera Avalon Streaming Components with Simulink HDL Coder. (fpga, vhdl, verilog)

Block-to-Code Highlighting Message

Code Generation Report for avalon_st_edge

Code Generation Report for avalon_st_edge

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updated almost 4 years ago

CORDIC atan calculation by Atsushi Matsumoto

CORDIC arctangent(atan) Simulink model. You can generate HDL from this model. (cordic, atan, arc)

cordic_atan_iterative_fxpt

cordic_atan_serial_fxpt

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updated almost 6 years ago

FWR Toolbox by HILAIRE Thibault

Toolbox for the Optimal Finite Word Length implementation of digital filters/controllers. (signal processing, control design, implementation)

DFIq2FWR( H )

FFT2FWR(n, toSimplify)

Modaldelta2FWR.m

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updated almost 6 years ago

BFSK design using system generator by KONSTANTINOS VOSKAKIS

BFSK transceiver using SysGen 10.1 (system generator 101, xilinx, bfsk)

pre(d)

preamble_detacher(clock,prbl_end,input_bit)

state_machine(din,reset)

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updated 6 years ago

Computing "mod" using embedded MATLAB by Kiran Kintali

This demo shows how to use embedded MATLAB to compute mod3 of a number in a hardware friendly fashio (embedded matlab, hdl, fpga)

mod_with_const

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updated 6 years ago

Modelling registers in Embedded MATLAB by Kiran Kintali

This example shows how to use Embedded MATLAB to model memory elements (embedded matlab, registers, hardware memory eleme...)

eml_delays_7a

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updated 6 years ago

Discrete Time Integrator in Embedded MATLAB by Kiran Kintali

This demo shows how to use Embedded MATLAB block parameters to control the algorithm behavior (embedded matlab, embedded matlab, discrete)

dti_eml_7a

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updated 6 years ago

Numerically Controlled Oscillator using Embedded MATLAB by Kiran Kintali

This demo shows how to model a fixed point NCO using an embedded MATLAB block (embedded matlab, nco, embedded matlab)

eml_nco_7b

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updated 6 years ago

Cordic Implementation of Sin/Cos using embedded MATLAB by Kiran Kintali

This model implements cordic algorithm using embedded MATLAB blocks (embedded matlab, cordic, fpga)

hdlcordic_eml

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updated 6 years ago

DSP algorithms using Embedded MATLAB Block by Kiran Kintali

using Embedded MATLAB block effectively in Simulink (embedded matlab, dsp, fpga)

viterbi_eml

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updated 6 years ago

Adaptive median filter using Embedded MATLAB by Kiran Kintali

This demo shows how to implement an adapative median filter in hardware (embedded matlab, embedded matlab, median filter)

get_center_data(min,med,max,center_data)

get_median(inbuf)

get_median_1d(inbuf)

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updated 6 years ago

Video Surveillance System Design with Simulink® and Xilinx® FPGAs by Alan Hwang

Files for the joint MathWorks and Xilinx seminar: Video Surveillance System Design (video, fpga, system)

rgb2bayer(filename, sensoralign)

init.m

init.m

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updated almost 9 years ago

Model-Based Design and FPGA Implementation with Simulink by Ali Behboodian

We introduce Simulink® for Model-Based Design in the context of FPGA implementation and verificatio (hardware targets, fpga, vhdl)

edgecmds

edgecmds_v

example_sel2html(fn)

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