HDL Verifier Support Package for Xilinx FPGA Boards by MathWorks HDLVerifier Team

HDL Verifier Support Package installer file that works with Support package installer (aerospace, communications, control design)

XILINXBRAM - Xilinx FPGA Block RAM Init by Stepan Matejka

Matlab code for Xilinx FPGA (Spartan, Virtex) 18k block RAM declaration using VHDL or Verilog (data export, xilinx, block ram)

xilinxbram(filename, dataary, bitsperitem, archname, primna...

xilinxbraminit

BFSK design using system generator by KONSTANTINOS VOSKAKIS

BFSK transceiver using SysGen 10.1 (system generator 101, xilinx, bfsk)

pre(d)

preamble_detacher(clock,prbl_end,input_bit)

state_machine(din,reset)

BFSK design using system generator by KONSTANTINOS VOSKAKIS

BFSK transmitter using System Generator 10.1 (system generator, bfsk, xilinx)

transmitter_model_final

Direct Digital Synthesis in XSG by Luis Moreno

Applications of CORDIC algorithm (cordic, dds, system generator)

ddscordic

CORDIC in XSG by Luis Moreno

Calculation of trigonometrical(sin and cos) functions by CORDIC (cordic, xilinx)

cordicsincos

Model-Based Design and FPGA Implementation with Simulink by Ali Behboodian

We introduce Simulink® for Model-Based Design in the context of FPGA implementation and verificatio (fpga, vhdl, xilinx)

edgecmds

edgecmds_v

example_sel2html(fn)