Automatic Hardware Implementation of Digital Filters for an Audio Codec

http://www.mathworks.com/company/newsletters/digest/2009/sept/audio-codec.html

First submitted by Linda Webb on 8 Oct 2009

With MathWorks tools, Mediatek can reduce the RTL code development cycle from 3 months to 2 weeks

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Date	Contributor	Description	Rating
8 Oct 2009	Linda Webb	Engineering an audio codec filter chain requires a careful balance of performance, power, and size. Our group must design solutions that not only meet rigorous standards for signal-to-noise ratio (SNR) and total harmonic distortion (THD), but also minimize power consumption and the total area of silicon required on the chip. We used to implement our designs by hand-writing Register Transfer Level (RTL) code. While this approach produces a relatively small chip area, it leads to long development times, and any subsequent changes to requirements can result in sig¬nificant rework of the implementation. This approach also carries some risk from a business perspective: We often do not know how difficult it will be to place and route the design until the very end of the design process, when it is all but impos¬sible to make changes and still meet our release date. We have adopted a new approach, one in which we design in MATLAB® and use Filter Design HDL Coder™ to generate synthesizable RTL code. By connecting system design to silicon, this approach enables us to rapidly evaluate filter archi¬tectures and optimize for silicon area. It has reduced our RTL code development cycle from three months to less than two weeks. System modifications that used to take almost a month to complete can now be made in as little as three days. By MediaTek Inc. This article was published in MATLAB Digest, September 2009

8 Oct 2009

Linda Webb

Engineering an audio codec filter chain requires a careful balance of performance, power, and size. Our group must design solutions that not only meet rigorous standards for signal-to-noise ratio (SNR) and total harmonic distortion (THD), but also minimize power consumption and the total area of silicon required on the chip.
We used to implement our designs by hand-writing Register Transfer Level (RTL) code. While this approach produces a relatively small chip area, it leads to long development times, and any subsequent changes to requirements can result in sig¬nificant rework of the implementation. This approach also carries some risk from a business perspective: We often do not know how difficult it will be to place and route the design until the very end of the design process, when it is all but impos¬sible to make changes and still meet our release date.
We have adopted a new approach, one in which we design in MATLAB® and use Filter Design HDL Coder™ to generate synthesizable RTL code. By connecting system design to silicon, this approach enables us to rapidly evaluate filter archi¬tectures and optimize for silicon area. It has reduced our RTL code development cycle from three months to less than two weeks. System modifications that used to take almost a month to complete can now be made in as little as three days.

By MediaTek Inc.

This article was published in MATLAB Digest, September 2009

Tag Activity

Tag	Applied By	Date/Time
paper	Linda Webb	8 Oct 2009 at 11:18am
article	Linda Webb	8 Oct 2009 at 11:18am
whitepaper	Linda Webb	8 Oct 2009 at 11:18am
hdl	Linda Webb	8 Oct 2009 at 11:18am
verilog	Linda Webb	8 Oct 2009 at 11:18am
fir filter	Linda Webb	8 Oct 2009 at 11:18am
signal processing	Linda Webb	8 Oct 2009 at 11:18am
dsp	Linda Webb	8 Oct 2009 at 11:18am
rtl code	Linda Webb	8 Oct 2009 at 11:18am
filter design	Linda Webb	8 Oct 2009 at 11:18am
audio codec	Linda Webb	8 Oct 2009 at 11:18am

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