At Mediatek, modifications that used to take almost a month are now completed in three days
|15 Dec 2009||Linda Webb||
Engineering an audio codec filter chain requires a careful balance of performance, power, and size. Our group must design solutions that not only meet rigorous standards for signal-to-noise ratio (SNR) and total harmonic distortion (THD), but also minimize power consumption and the total area of silicon required on the chip.
We used to implement our designs by hand-writing Register Transfer Level (RTL) code. While this approach produces a relatively small chip area, it leads to long development times, and any subsequent changes to requirements can result in significant rework of the implementation. This approach also carries some risk from a business perspective: We often do not know how difficult it will be to place and route the design until the very end of the design process, when it is all but impossible to make changes and still meet our release date.
We have adopted a new approach, one in which we design in MATLAB® and use Filter Design HDL Coder™ to generate synthesizable RTL code. By connecting system design to silicon, this approach enables us to rapidly evaluate filter architectures and optimize for silicon area. It has reduced our RTL code development cycle from three months to less than two weeks. System modifications that used to take almost a month to complete can now be made in as little as three days.
By MediaTek, Inc
This article was published in The MathWorks News & Notes, 2009