Thread Subject: how to realize this block in simulink?

The inputs are discrete signal A and B. I want the output be
a vector containing A repeating B times. For instance, at
one sample, A=2, B=3; then the output should be [2,2,2].

On Nov 29, 2:08 pm, "faming " <lifam...@gmail.com> wrote:
> The inputs are discrete signal A and B. I want the output be
> a vector containing A repeating B times. For instance, at
> one sample, A=2, B=3; then the output should be [2,2,2].

As far as I know this cannot be done. When your B input changes the
block's output port width also needs to change and this is not
possible with Simulink. Port widths are fixed during the block's
initialization routines and cannot be altered after that.

Ashish.

Praetorian <ashish.sadanandan@gmail.com> wrote in message
<86047125-4d7b-4cd1-a19f-b45e1f5643a0@s36g2000prg.googlegroups.com>...
> On Nov 29, 2:08 pm, "faming " <lifam...@gmail.com> wrote:
> > The inputs are discrete signal A and B. I want the output be
> > a vector containing A repeating B times. For instance, at
> > one sample, A=2, B=3; then the output should be [2,2,2].
>
> As far as I know this cannot be done. When your B input
changes the
> block's output port width also needs to change and this is not
> possible with Simulink. Port widths are fixed during the
block's
> initialization routines and cannot be altered after that.
>
> Ashish.

You can create a signal that is fed by differing width
vectors, but simulink will just treat the final product as
having the width necssary to handle all signals. Switch
between a 1d and 2d input and the output is considered 2d.

But perhaps the OP was looking for a method that repeated a
value for a certain number of samples. For example, at time
0, a=2, b=3 means that the function outputs 2 for the next 3
samples?

-Chris