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Hi,
I have a question regarding the suppression of SMIs. Our target PC mainboard contains an ICH8M-E chipset. To suppress SMIs we added the correspondig chipset device to the SMI disabling s-function provided on the exchange server, which was originally written for ICH5 chipsets. Unfortunately there seems to be at least one SMI source that still sends an interrupt and activates the GBL_SMI_EN bit again during runtime resuling in TET overloads. The documentation of the ICH8 chipset (http://www.intel.com/assets/pdf/datasheet/313056.pdf) contains a note on page 408, that the GBL_SMI_EN bit can be locked by a SMI_LOCK bit. Setting this SMI_Lock bit during model initialization phase could perhaps help us to suppress the SMIs, because the interrput source would not be able to switch the GBL_SMI_EN bit during runtime anymore. Does anybody know if it is possible to set this SMI_LOCK bit using xPC
I/O port output functions like xpcOutpDW and how to adress this bit, respectively?
Thanks in advance.
Steffen
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