Communications Blockset 4.3

Fractional-N Frequency Synthesis

This demo shows how to simulate a phase-locked fractional-N frequency synthesizer. The model multiplies the frequency synFr of a reference signal by a constant synN+synM, to produce a synthesized signal of frequency synFr(synN+synM). A feedback loop maintains the frequency of the synthesized signal at this level.

This demo is similar to the PLL-Based Frequency Synthesis Demo, which produces a synthesized signal of frequency synFr*synN/synM, where synN and synM are integers. In this demo, synN is an integer and synM is a fraction between 0 and 1. This approach has several advantages, since it enables you to approximate the frequency of the synthesized signal with relatively small values for synN and synM. It also enables you to use a larger reference frequency. For more information, see Selected Bibliography.

Contents

Structure of the Demo

The model uses these variables in addition to synN and synM:

The model initially assigns values to these variables as follows:

The frequency of the synthesized signal at the model's steady state is then 103 MHz. After running the simulation with these values, you can later change them by typing new values in the MATLAB® Command Window, if you want to experiment with the model.

Blocks and Subsystems in the Demo

Most of the blocks in this model function in the same way as they do in the PLL-Based Frequency Synthesis Demo. Two subsystems in this example are not present in the Phase-Locked Frequency Synthesis demo: Accumulator and Divide Frequency. This section also discusses the phase detector in this demo.

Accumulator. The Accumulator subsystem repeatedly adds the constant synM to a cumulative sum. While the sum is less than 1, the output labeled Carry is 0. At a time step when the sum becomes greater than or equal to 1, the carry output is 1 and the cumulative sum is reset to its fractional part. The fraction of the time when the carry output is 1 is equal to synM, while the fraction of the time when it is 0 is equal to 1-*synM*.

Divide Frequency. The Divide Frequency subsystem divides the frequency of the synthesized signal by synN when the output of the Accumulator subsystem is 0, and divides it by synN+1 when the output is 1. As a result, the average amount that frequency is divided by is

(1-synM)*synN + synM*(synN+1) = synN + synM = 10.3

The line leading out of the Divide Frequency subsystem is labeled Divided synthesized. At steady state, when the frequency of the synthesized signal is 103 MHz, the divided synthesized signal has an average frequency of 10 Mhz.

Phase Detector. The Logical Operator block acts as a phase detector. It applies the XOR operation to the frequencies of the reference signal and the frequency of the output from the Divide Frequency subsystem.

At steady state, the block's output is a pulse train with frequency of 20 MHz. The reason for this is that both inputs to the block have an average frequency of 10 MHz, but they are out of phase by 1/4 of their period. As a result, the signal after the XOR operation is a periodic pulse train with an average frequency of 20 MHz.

You can view the signals these blocks generate by double-clicking the block labeled Scope at the top of the model window.

Results and Displays

When you run a simulation, scope window display

Selected Bibliography

Egan, William F., Frequency Synthesis by Phase Lock, Second Ed., N.Y., John Wiley & Sons, 2000.