Third-Party Products & Services
The ispLEVER design suite is a comprehensive design environment for Lattice FPGA devices, including design entry, implementation, verification, debugging, and device programming.This illustration shows a typical design flow using MathWorks tools in conjunction with Lattice ispLeverDSP flow and the ispLEVER FPGA design tool. Designers use Simulink to model the system using graphical blocks that are easily applied and changed as necessary to obtain desired results. The ispLeverDSP software produces a VHDL test bench to verify the results. The ispLEVER design suite is a comprehensive FPGA design environment for design entry, implementation, verification, debugging, and device programming.
For maximum performance and value, the LatticeECPTM-DSP FPGA combines an efficient FPGA fabric with dedicated high-performance DSP blocks on-chip. The Lattice ECP-DSP FPGA is ideal for use in applications where you need cost-effective DSP functionality. Such applications include software-defined radio, wireless communications, military applications, and video processing equipment. MATLAB and Simulink users can take advantage of the close integration between these tools and Lattice's comprehensive ispLEVER tool suite and ispLeverDSP design flow to build DSP application hardware faster, better, and at lower costs.