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Riviera is a high-performance ASIC and large FPGA verification solution that is optimized for long simulation runs and batch processing. It is a stand-alone VHDL, Verilog, and EDIF simulation environment that integrates seamlessly with other tools available on the market.
The interface included in Riviera enables users to execute MATLAB commands, call M-functions, and transfer data to or from the MATLAB workspace. All operations are controlled from the HDL code. Communication with MATLAB is accomplished through a dedicated set of subprograms prepared for both Verilog and VHDL. At any level of a design hierarchy, the user can pass commands to MATLAB (for example, pass an expression to solve or call an M-function), transfer HDL variables to the MATLAB workspace, perform necessary operations, and transfer the results back to the HDL simulator.
The Simulink interface enables users to co-simulate functional blocks described with mathematical formulas and behavioral models described with hardware description languages. The interface is accompanied by the Co-Simulation wizard for Simulink that generates a black-box representation for any HDL or EDIF unit compiled to a Riviera library. Black-boxes generated by the wizard can be placed on Simulink diagrams and used in the verification process performed within Simulink. Using the wizard, the user sets the options required for the co-simulation of black-boxes, such as the clock and clock enable ports, quantization, etc.