EDA Simulator Link

EDA Simulator Link™ provides a verification interface between MATLAB^® or Simulink^® and your HDL simulator or FPGA board. Using EDA Simulator Link you can verify a Verilog^® or VHDL^® design against your Simulink model or MATLAB algorithm using cosimulation with a Verilog or VHDL simulator, such as Mentor Graphics^® ModelSim^® or Cadence^® Incisive^®. EDA Simulator Link also lets you perform hardware verification on your FPGA board using FPGA-in-the-loop simulation.

With EDA Simulator Link you can use MATLAB code and Simulink models as a test bench that generates stimulus for an HDL design and analyzes the simulation's response. You can replace HDL design components with MATLAB code and Simulink models, enabling simulation of the complete system before all the HDL design elements are available.

EDA Simulator Link lets you create transaction-level model (TLM) components for use in virtual prototyping environments.