EDA Simulator Link 3.0

Introduction

EDA Simulator Link™ is a cosimulation interface that provides a bidirectional link between MATLAB® and Simulink® and HDL simulators from Mentor Graphics, Cadence, and Synopsys, enabling verification of VHDL®, Verilog®, and mixed-language implementations.

EDA Simulator Link lets you use MATLAB code or Simulink models as a test bench that generates stimulus for an HDL simulation and analyzes the simulation’s response. It also lets you replace multiple HDL components with MATLAB code or Simulink models, enabling simulation of the complete system before all the HDL design elements are available.

EDA Simulator Link enables interactive and batch-mode cosimulation on a single computer, across heterogeneous platforms, or across a network.

Key Features

• Full VHDL, Verilog, and mixed-language cosimulation support for MATLAB or Simulink
• Test bench capability, enabling the use of MATLAB code or Simulink models to stimulate HDL code and check its response
• Component capability, enabling simulation of MATLAB code or Simulink models in place of entities not yet coded in HDL
• Cross-platform cosimulation using MATLAB or Simulink on one platform and the HDL simulator on a different platform
• Interactive or batch-mode cosimulation, debugging, testing, and verification of HDL code
• Single-machine, multiple-machine, and cross-network cosimulation using shared-memory or TCP/IP-socket communication modes

Elaboration of a floating-point reference algorithm and verification of a Verilog implementation using a cosimulation interface.