EDA Simulator Link 3.4

Latest Features

Released: 1 Sep 2011

Version 3.4, part of Release 2011b, includes the following enhancements:

FPGA-in-the-Loop (FIL) simulation available through the HDL Workflow Advisor in Simulink^® HDL Coder™
Unlimited-sized vector input and output ports for FIL
Model reference and variable step solver support in FPGA-in-the-Loop simulations

See the Release Notes for details.

Released: 8 Apr 2011

Version 3.3, part of Release 2011a, includes the following enhancements:

FPGA-in-the-loop simulation using Xilinx Spartan-6, Virtex-6, Virtex-5, and Virtex-4 devices on a variety of development boards, including SP605, SP601, ML605, ML401/2/3, ML506/7, XUP Atlys, and XUPV5

See the Release Notes for details.

Released: 3 Sep 2010

Version 3.2, part of Release 2010b, includes the following enhancements:

New EDA Cosimulation Assistant for automating the import of HDL code to produce a customized block or function
64-bit Windows^® support for HDL cosimulation
Generation of Visual Studio^® project for generated TLM components
Xilinx^® ISE^® project and clock module generation for use with Filter Design HDL Coder™

See the Release Notes for details.

Released: 5 Mar 2010

Version 3.1, part of Release 2010a, includes the following enhancements:

Support for batch and command-line cosimulation modes
Export of Simulink algorithm models as OSCI TLM 2.0 components
Generation of standalone SystemC test bench for generated TLM 2.0 component
Generation of Xilinx^® ISE projects for FPGA designs
Support for direct feedthrough mode to eliminate cosimulation latency in combinational HDL paths

See the Release Notes for details.

Released: 4 Sep 2009

Version 3.0, part of Release 2009b, includes minor enhancements. See the Release Notes for details.