Filter Design HDL Coder™ 2.2

Learn more about Filter Design HDL Coder™ through product demos and online seminars that highlight features or application examples.

HDL Butterworth Filter This demonstration illustrates how to generate HDL code for a 5th order Butterworth filter. The cutoff-frequency for this filter is very low relative to the sample rate, leading to a filter that is difficult to make practical.   HDL Inverse Sinc Filter This demonstration illustrates how to generate HDL code for an inverse sinc (sin x/x) peaking filter that adds preemphasis to compensate for the inherent sinc response of the digital-to-analog converter (DAC).   HDL Minimum Phase FIRT Filter This demonstration illustrates how to generate HDL code for a minimum phase FIRT filter with 10-bit input data and 10-bit output data.   HDL Tone Control Filter Bank This demonstration illustrates how to generate HDL code for bank of 24 first-order shelving filters that implement an audio tone control with 1 dB steps from -6 dB to +6 dB for bass and treble.   HDL Video Filter This demonstration illustrates how to generate HDL code for an ITU-R BT.601 luma filter with 8-bit input data and 10-bit output data.   HDL Digital-Up Converter This demonstration illustrates how to generate HDL code for a Digital-Up Converter (DUC). A DUC is a digital circuit which converts a digital baseband signal to a passband signal.   HDL Filter Link This demo shows how to use FDATool to design a filter, generate a structural model of the filter in Simulink®, and generate HDL. It also shows how to use an HDL simulator to cosimulate the Simulink behavioral model and the generated HDL.   HDL Programmable FIR Filter   This demonstration illustrates how to generate HDL code for an FIR filter with a processor interface for loading coefficients.   HDL Generation for HDL Filters   This demonstration illustrates Model-Based Design for a fixed-point filter for implementation on FPGA or ASIC hardware. We will automatically generate synthesizable HDL and verify implementation through cosimulation with ModelSim   HDL Serial Architectures for FIR Filters   This demonstration illustrates how to generate HDL code for a symmetrical FIR filter with fully parallel, fully serial, partly serial and cascade-serial architectures for a lowpass filter for an audio filtering application.   HDL Fractional Delay (Farrow) Filter   This demonstration illustrates how to generate HDL code for a fractional delay (Farrow) filter for timing recovery in a digital modem. View All Demos Trial Software Available Licensed Users: Download a 15-day trial of most MathWorks products (login required). Don't Have a License? Request trial software and a MathWorks representative will call to get you started.