Filter Design HDL Coder 2.5

HDL Digital Up-Converter (DUC)

This demonstration illustrates how to generate HDL code for a Digital-Up Converter (DUC). A DUC is a digital circuit which converts a digital baseband signal to a passband signal. The input baseband signal is sampled at a relatively low sampling rate, typically the digital modulation symbol rate. The baseband signal is filtered and converted to a higher sampling rate before modulating a direct digitally synthesized (DDS) carrier frequency.

The input signals are passed through three filtering stages. Each stage first filters the signals with a lowpass interpolating filter and then performs a sampling rate change. The DUC in this demo is a cascade of two FIR Interpolation Filters and one CIC Interpolation Filter. The first FIR Interpolation Filter is a pulse shaping FIR filter that increases the sampling rate by 2 and performs transmitter Nyquist pulse shaping. The second FIR Interpolation Filter is a compensation FIR filter that increases the sampling rate by 2 and compensates for the distortion of the following CIC filter. The CIC Interpolation Filter increases the sampling rate by 32.

The filters are implemented in fixed-point mode. The input/output word length and fraction length are specified. The internal settings of the first two filters are specified, while the internal settings of the CIC filter are calculated automatically to preserve full precision.

Contents

Create Pulse Shaping FIR Filter

Create a 32-tap FIR Interpolator with interpolation factor of 2. The wordlength and fraclength are set to 16, 15 for input, output and internal settings.

pfir = [0.0007    0.0021   -0.0002   -0.0025   -0.0027    0.0013    0.0049  
  0.0032 ...
       -0.0034   -0.0074   -0.0031    0.0060    0.0099    0.0029   -0.0089  
 -0.0129 ...
       -0.0032    0.0124    0.0177    0.0040   -0.0182   -0.0255   -0.0047  
  0.0287 ...
        0.0390    0.0049   -0.0509   -0.0699   -0.0046    0.1349    0.2776  
  0.3378 ...
        0.2776    0.1349   -0.0046   -0.0699   -0.0509    0.0049    0.0390  
  0.0287 ...
       -0.0047   -0.0255   -0.0182    0.0040    0.0177    0.0124   -0.0032  
 -0.0129 ...
       -0.0089    0.0029    0.0099    0.0060   -0.0031   -0.0074   -0.0034  
  0.0032 ...
        0.0049    0.0013   -0.0027   -0.0025   -0.0002    0.0021    0.0007 ]
;

hpfir = mfilt.firinterp(2, pfir);
set(hpfir, ...
    'arithmetic', 'fixed', ...
    'filterinternals', 'specifyprecision', ...
    'roundmode', 'nearest', ...
    'inputwordlength', 16, ...
    'inputfraclength', 15, ...
    'coeffwordlength', 16, ...
    'outputwordlength', 16, ...
    'outputfraclength', 15, ...
    'accumwordlength', 16, ...
    'accumfraclength', 15);

Create Compensation Fir Filter

Create an 11-tap FIR Interpolator with interpolation factor of 2. The wordlength and fraclength are set to 16, 15 for input, output and internal settings.

cfir = [-0.0007   -0.0009    0.0039    0.0120    0.0063   -0.0267   -0.0592 
  -0.0237 ...
         0.1147    0.2895    0.3701    0.2895    0.1147   -0.0237   -0.0592 
  -0.0267 ...
         0.0063    0.0120    0.0039   -0.0009   -0.0007];

hcfir = mfilt.firinterp(2, cfir);
set(hcfir, ...
    'arithmetic', 'fixed', ...
    'filterinternals', 'specifyprecision', ...
    'roundmode', 'nearest', ...
    'inputwordlength', 16, ...
    'inputfraclength', 15, ...
    'coeffwordlength', 16, ...
    'outputwordlength', 16, ...
    'outputfraclength', 15, ...
    'accumwordlength', 16, ...
    'accumfraclength', 15);

Create CIC Interpolating Filter

Create a 5-stage CIC Interpolator with interpolation factor of 32. The input wordlength and fraclength are set to 16, 15. The output wordlength is set to 20. The output fraclength and filter internals are calculated automatically to preserve full precision.

hcic = mfilt.cicinterp(32, 1, 5, 16, 20);
hcic.inputfraclength = 15;

Cascade of the Filters

Create a cascade filter including the above three filters. Check the frequency response of the cascade filter.

hduc = cascade(hpfir, hcfir, hcic);
fvtool(hduc);

Generate VHDL Code for DUC

Generate synthesizable and portable VHDL code for the cascade filter.

You have the option of generating a VHDL, Verilog, or ModelSim® .do file test bench to verify that the HDL design matches the MATLAB® filter.

To generate Verilog instead of VHDL, change the value of the property 'TargetLanguage', from 'VHDL' to 'Verilog'.

workingdir = tempname;
generatehdl(hduc,'Name', 'hdlduc', 'TargetLanguage', 'VHDL',...
            'TargetDirectory', workingdir);

Warning: Using the SumFormat for a product stage in fir to be compatible wit
h
MATLAB filter.
Warning: Using the SumFormat for a product stage in fir to be compatible wit
h
MATLAB filter.
Warning: Using the SumFormat for a product stage in fir to be compatible wit
h
MATLAB filter.
### Starting VHDL code generation process for filter: hdlduc
### Cascade stage # 1
Warning: Using the SumFormat for a product stage in fir to be compatible wit
h
MATLAB filter.
### Starting VHDL code generation process for filter: hdlduc_stage1
### Generating: C:\TEMP\R2009bd_340_2732\tp0fe99327_9997_4de0_856c_98ee12ca1
123\hdlduc_stage1.vhd
### Starting generation of hdlduc_stage1 VHDL entity
### Starting generation of hdlduc_stage1 VHDL architecture
### HDL latency is 1 samples
### Successful completion of VHDL code generation process for filter: hdlduc
_stage1

### Cascade stage # 2
Warning: Using the SumFormat for a product stage in fir to be compatible wit
h
MATLAB filter.
### Starting VHDL code generation process for filter: hdlduc_stage2
### Generating: C:\TEMP\R2009bd_340_2732\tp0fe99327_9997_4de0_856c_98ee12ca1
123\hdlduc_stage2.vhd
### Starting generation of hdlduc_stage2 VHDL entity
### Starting generation of hdlduc_stage2 VHDL architecture
### HDL latency is 1 samples
### Successful completion of VHDL code generation process for filter: hdlduc
_stage2

### Cascade stage # 3
### Starting VHDL code generation process for filter: hdlduc_stage3
### Generating: C:\TEMP\R2009bd_340_2732\tp0fe99327_9997_4de0_856c_98ee12ca1
123\hdlduc_stage3.vhd
### Starting generation of hdlduc_stage3 VHDL entity
### Starting generation of hdlduc_stage3 VHDL architecture
### Section # 1 : Comb
### Section # 2 : Comb
### Section # 3 : Comb
### Section # 4 : Comb
### Section # 5 : Comb
### Section # 6 : Integrator
### Section # 7 : Integrator
### Section # 8 : Integrator
### Section # 9 : Integrator
### Section # 10 : Integrator
### HDL latency is 32 samples
### Successful completion of VHDL code generation process for filter: hdlduc
_stage3

### Generating: C:\TEMP\R2009bd_340_2732\tp0fe99327_9997_4de0_856c_98ee12ca1
123\hdlduc.vhd
### Starting generation of hdlduc VHDL entity
### Starting generation of hdlduc VHDL architecture
### HDL latency is 225 samples
### Successful completion of VHDL code generation process for filter: hdlduc

Generate VHDL Test Bench

Generate a stimulus signal for the filter. The length of the stimulus should be greater than the total latency of the filter. Be sure to remove the default stimuli by setting the value to empty.

Generate a VHDL test bench to verify that the results match the MATLAB results exactly.

t = 0.005:0.005:1.5;
stim = chirp(t, 0, 1, 150);
generatetb(hduc, 'vhdl', 'TestBenchUserStimulus', stim, ...
           'TestBenchStimulus', [],...
           'TargetDirectory', workingdir);

### Starting generation of VHDL Test Bench
Warning: Using the SumFormat for a product stage in fir to be compatible wit
h
MATLAB filter.
Warning: Using the SumFormat for a product stage in fir to be compatible wit
h
MATLAB filter.
Warning: Using the SumFormat for a product stage in fir to be compatible wit
h
MATLAB filter.
### Generating input stimulus
### Done generating input stimulus; length 300 samples.
### Generating Test bench: C:\TEMP\R2009bd_340_2732\tp0fe99327_9997_4de0_856
c_98ee12ca1123\hduc_tb.vhd
### Please wait ...
### Done generating VHDL Test Bench

ModelSim® Simulation Results

The following display shows the ModelSim HDL simulator running these test benches.

DUC response to the a chirp stimulus:

Conclusion

In this demonstration, you designed three individual interpolation filters, cascaded them into a Digital-Up Converter, verified the frequency response of the filter, and called Filter Design HDL Coder™ functions to generate VHDL code for the filter and a VHDL test bench to verifyied the VHDL code against its MATLAB result. The simulation result of the VHDL code proved that the generated VHDL filter produced a bit-true implementation of the MATLAB filter.