Filter Design HDL Coder 2.9

Latest Features

Version 2.9

Released: 1 Sep 2011
 

Version 2.9, part of Release 2011b, includes the following enhancements:

• HDL code generation for digital-up and digital-down converter System objects
• Multiplier pipelining extended to serial implementations
• Serial implementations for IIR Filter (Direct form II second order sections)

See the Release Notes for details.

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Version 2.8

Released: 8 Apr 2011
 

Version 2.8, part of Release 2011a, includes the following enhancements:

• HDL code generation for partly serial architectures for IIR DF1-SOS and for FIR interpolators
• HDL code generation for distributed arithmetic and serial architectures for cascade filters

See the Release Notes for details.

Version 2.7

Released: 3 Sep 2010
 

Version 2.7, part of Release 2010b, includes the following enhancements:

• Support for variable-rate cascaded integrator comb (CIC) filters
• Simplified way of specifying distributed-arithmetic architecture for FIR filters
• Xilinx ISE^® project and clock module generation (requires EDA Simulator Link™)

See the Release Notes for details.

Version 2.6

Released: 5 Mar 2010
 

Version 2.6, part of Release 2010a, includes the following enhancements:

• Programmable options for multiplier pipelining for FIR filters
• Support for partly serial architecture for FIR decimators
• Option to suppress reset logic generation for shift registers

See the Release Notes for details.

Version 2.5

Released: 4 Sep 2009
 

Version 2.5, part of Release 2009b, includes the following enhancements:

• Support for RAM-based programmable coefficients for single-rate FIR filters
• Expanded support for complex input data and coefficients, including all IIR SOS filters and FIR filters
• Generation of a Simulink model for cosimulation of generated HDL code

See the Release Notes for details.