The generated code is in bit-true agreement with your model, enabling your design to perform as it did in simulation. The generated code automatically handles all the details of implementing fixed-point designs, such as scaling adjustment, rounding, and advanced fixed-point math. You can generate code for signals and parameters with word sizes from 1 to 128 bits. You can use the generated code for a variety of applications, including accelerated simulation, rapid prototyping, and production deployment.
Using Fixed-Point Designer with HDL Coder™, you can generate bit-true synthesizable Verilog® and VHDL® code from your fixed-point MATLAB code, Simulink models, and Stateflow charts.