HDL Coder lets you generate synthesizable HDL code for FPGA and ASIC implementations in a few steps:
The HDL Workflow Advisor in HDL Coder automatically converts MATLAB code from floating-point to fixed-point and generates synthesizable VHDL and Verilog code. This capability lets you model your algorithm at a high level using abstract MATLAB constructs and System objects while providing options for generating HDL code that is optimized for hardware implementation. HDL Coder provides a library of ready-to-use logic elements, such as counters and timers, which are written in MATLAB.
The HDL Workflow Advisor generates VHDL and Verilog code from Simulink and Stateflow. With Simulink, you can model your algorithm using a library of more than 200 blocks, including Stateflow charts. This library provides complex functions, such as the Viterbi decoder, FFT, CIC filters, and FIR filters, for modeling signal processing and communications systems and generating HDL code.
In MATLAB or Simulink, you can optimize HDL code to achieve speed-area objectives by employing distributed pipelining, streaming, and resource sharing. In MATLAB, you can use advanced loop optimizations, such as loop streaming and loop unrolling, for a MATLAB design containing for-loops or matrix operations. You can map a persistent array or matrix variables in MATLAB code to block RAMs. In Simulink, you can implement multichannel designs and serialization techniques common to signal processing and multimedia applications.
Resource Sharing For Area Optimization (Example)
The HDL Workflow Advisor in HDL Coder automates the workflow for implementing your MATLAB algorithms and Simulink models into Xilinx and Altera FPGAs. The HDL Workflow Advisor integrates all steps of the FPGA design process, including:
You can view a postsynthesis timing report and back annotate the Simulink model to identify timing-constraint bottlenecks. This integration with synthesis tools enables rapid design iterations and significantly reduces FPGA design cycle time.
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HDL Coder generates VHDL and Verilog test benches for rapid verification of generated HDL code. You can customize an HDL test bench using a variety of options that apply stimuli to the HDL code. You can also generate script files to automate the process of compiling and simulating your code in HDL simulators.
HDL Coder works with HDL Verifier to automatically generate two types of cosimulation models:
HDL Coder documents generated code in an HTML report that contains hyperlinked HDL code and a table of generated HDL files. Hyperlinks in the HDL code let you navigate to the corresponding MATLAB algorithm or Simulink blocks that generated the code.
HDL Coder supports code traceability for high-integrity applications that adhere to standards su ch as DO-254 by enabling you to:
Using Simulink Verification and Validation™ with HDL Coder enables you to embed system requirements as comments within HDL code generated from Simulink or Stateflow. As a result, you can achieve complete transparency throughout the entire workflow, from system requirements to generated HDL code.
The development processes used for industrial FPGA and ASIC applications, such as DO-254 in the aerospace industry, may recommend the use of certain RTL coding guidelines. HDL Coder seeks to generate VHDL and Verilog code that meets common industry coding guidelines such as RMM and STARC. HDL Coder also generates reports that help you identify unsuitable constructs in your Simulink models and MATLAB code so that you can adapt your models to get generated RTL that satisfies these coding guidelines.
HDL Coder can also generate third-party lint tool scripts that can be used to check your generated HDL code. Code generated with HDL Coder can be checked with industry-standard lint tools like Atrenta SpyGlass, Real Intent Ascent Lint, Synopsys Leda, and Mentor Graphics HDL Designer. HDL Coder generates custom scripts that allow integration with any lint tool.
Code generated using HDL Coder follows RTL coding principles by:
Achieving STARC and DO-254 Compliance Using HDL Coder Generated Code (Technical Article)