HDL Coder
Generate VHDL and Verilog code for FPGA and ASIC designs
Product Overview 1:55
HDL Coder™ generates portable, synthesizable VHDL® and Verilog® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.
HDL Coder provides a workflow advisor that automates the programming of Xilinx® and Altera® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated HDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
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MATLAB, Simulink, and HDL Coder are indispensable for us because we simulate, debug, and verify our design as an executable specification and then generate the initial HDL in almost no time.