HDL Coder
Generate VHDL and Verilog code for FPGA and ASIC designs
Product Overview 1:55
HDL Coder™ generates portable, synthesizable VHDL® and Verilog® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.
HDL Coder provides a workflow advisor that automates the programming of Xilinx® and Altera® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated HDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
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For development of the world’s first highly optimized digital audio hub solution, Simulink and Simulink HDL Coder were the best options. The design and verification flow we applied using MathWorks tools scales well and provides the route to build more complex DSP and signal mixing paths.