HDL Coder 3.0

Latest Features

Version 3.0

Released: 1 Mar 2012
 

Version 3.0, part of Release 2012a, includes the following enhancements:

• Automated fixed-point HDL Code generation from MATLAB code and System objects
• Code generation from subsystems containing Xilinx^® System Generator blocks
• Turnkey workflow for Altera^® boards
• Instantiation of Xilinx and Altera floating-point IP
• Code generation from any level of hierarchy with user-controllable flattening
• Code generation for programmable coefficient and multiclock filters
• Code generation for HDL CRC Generator, Bus Creator, and Bus Selector Blocks

See the Release Notes for details.

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Version 2.2

Released: 1 Sep 2011
 

Version 2.2, part of Release 2011b, includes the following enhancements:

• FPGA-in-the-Loop (FIL) simulation available through the HDL Workflow Advisor
• RAM-based implementation for persistent variables in MATLAB Function block
• Block mask parameters generated as generics in VHDL or as parameters in Verilog
• Oversampling, streaming, and resource sharing that optionally generate multiple clocks
• Hierarchical distributed pipelining that preserves original system hierarchy

See the Release Notes for details.

Version 2.1

Released: 8 Apr 2011
 

See highlights and screen shots.

Version 2.1, part of Release 2011a, includes the following enhancements:

• Device support for 9 Xilinx FPGA development boards
• Enhanced area and speed optimizations, including resource sharing within feedback loops, retiming across subsystem hierarchies, path delay balancing, and resource estimation reports
• Additional clocking options that include generation of multiple clocks
• Code generation for From and Goto blocks connected across subsystem boundaries
• RAM-based implementations for Viterbi Decoder and Integer Delay blocks
• Save and restore feature in HDL Workflow Advisor
• BlackBox implementations for subsystems that enable specification of generic parameters as strings of parameter-value pairs

See the Release Notes for details.

Version 2.0

Released: 3 Sep 2010
 

Version 2.0, part of Release 2010b, includes the following enhancements:

• GUI support for specification of block implementations and implementation parameters
• Area optimization through serialization and resource sharing
• Resource utilization estimation and report
• Support for atomic subsystems to reduce the number of HDL files
• Expanded support for HDL code generation, including modulation, demodulation, interleaver, deinterleaver, and convolutional encoders
• Support of pipelined architectures for filter blocks, including Digital Filter, Discrete FIR Filter, FIR Decimation, FIR Interpolation, CIC Decimation, CIC Interpolation, and Biquad Filter

See the Release Notes for details.

Version 1.7

Released: 5 Mar 2010
 

Version 1.7, part of Release 2010a, includes the following enhancements:

• New HDL Workflow Advisor, unifying model configuration, code generation, FPGA synthesis, and post-synthesis critical path annotation of the model
• Option to minimize or remove the use of a clock enable signal in the generated code
• Expanded Simulink block support for HDL code generation, including Viterbi Decoder, BPSK/QPSK/M-PSK Modulators and Demodulators, Convolutional Interleaver and Deinterleaver, CORDIC sin, and cos
• Support for Serial architectures for Digital Filter, Discrete FIR Filter, and FIR Decimation blocks
• Support for distributed arithmetic architectures for FIR Decimation block
• Distributed pipelining support for Simulink subsystems

See the Release Notes for details.