HDL Verifier
Product Description
- Key Features
- HDL Cosimulation
- FPGA-in-the-Loop Verification
- Transaction-Level Model Support
- Use of HDL Verifier with HDL Coder
- Supported HDL Simulators and FPGA Boards
Key Features
- Cosimulation support for Cadence Incisive and for Mentor Graphics ModelSim and Questa
- FPGA-in-the-loop verification using Xilinx and Altera FPGA boards
- MATLAB functions and Simulink blocks
- Generation of IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models
- Interactive or batch-mode cosimulation and debugging
- Single-machine, multiple-machine, and cross-network cosimulation
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