HDL Verifier

Key Features

  • Cosimulation support for Cadence Incisive and for Mentor Graphics ModelSim and Questa
  • FPGA-in-the-loop verification using Xilinx and Altera FPGA boards
  • MATLAB functions and Simulink blocks
  • Generation of IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models
  • Interactive or batch-mode cosimulation and debugging
  • Single-machine, multiple-machine, and cross-network cosimulation
Next: HDL Cosimulation Test Benches

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Implementation of FPGA-Based Channelizers with MATLAB and Simulink

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