HDL Verifier

Use of HDL Verifier with HDL Coder

HDL Verifier works with HDL Coder to accelerate your FPGA and ASIC design and verification workflow. When you generate HDL code from HDL Coder, you can also generate an HDL cosimulation or FPGA-in-the-loop model.

HDL Verifier lets you integrate automatically generated code with your legacy HDL code using black-box integration. Together with HDL Coder, HDL Verifier completes the workflow for high-integrity applications that adhere to standards such as DO-254.

Using the FPGA-in-the-Loop Wizard to automatically generate an FGPA-in-the-loop model for video sharpening.
Using the FPGA-in-the-Loop Wizard to automatically generate an FPGA-in-the-loop (FIL) model for video sharpening. FIL simulation with HDL Coder lets you efficiently perform design space exploration, accelerate verification of your generated HDL code, and improve hardware implementation.
Next: Supported HDL Simulators and FPGA Boards

Try HDL Verifier

Get trial software

Accelerate Design Space Exploration Using HDL Coder Optimizations

View webinar