HDL Verifier

Key Features

  • Cosimulation support for Cadence Incisive and for Mentor Graphics ModelSim and Questa
  • FPGA-in-the-loop verification using Xilinx and Altera FPGA boards
  • MATLAB functions and Simulink blocks
  • Generation of IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models
  • Interactive or batch-mode cosimulation and debugging
  • Single-machine, multiple-machine, and cross-network cosimulation

HDL Cosimulation

HDL cosimulation with HDL Verifier lets you verify that your HDL code matches your MATLAB algorithm and Simulink models by providing visibility into the HDL code. You can assess how differences between expected results and HDL simulation could affect the design at the system level.

HDL Verifier provides an HDL Cosimulation Wizard that automatically connects Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators to MATLAB and Simulink.

Cosimulation in Simulink using the HDL Cosimulation Wizard.
Cosimulation in Simulink using the HDL Cosimulation Wizard. You can automate the HDL verification workflow and gain insight into how your design performs at the system level and the logic level.

FPGA-in-the-Loop Verification

HDL Verifier automates the implementation of HDL code on FPGA boards to enable FPGA-in-the-loop (FIL) verification, which complements HDL cosimulation by enabling you to run test scenarios faster. As a result you can explore more test cases and perform extensive regression testing on your designs. This approach also ensures that the algorithm will behave as expected in the real world.

HDL Verifier supports FIL verification over the Gigabit Ethernet interface for Xilinx and Altera FPGA boards. See a list of supprted hardware in the documentation.

Using FPGA-in-the-loop (FIL) verification to verify an HDL design.
Using FPGA-in-the-loop (FIL) verification to verify an HDL design. HDL Verifier supports Xilinx and Altera FPGA boards with Gigabit Ethernet for fast FPGA-based verification.

Using Custom Boards for FPGA-in-the-Loop Verification 2:17
Perform FPGA-based verification with custom boards using MATLAB® and Simulink® as test benches. Figures based on or adapted from figures and text owned by Xilinx, Inc. and used with permission. Copyright 2013 Xilinx, Inc.

Transaction-Level Model Support

When used with Simulink Coder, HDL Verifier automatically generates IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models. Generated SystemC models have a TLM 2.0 compliant interface with a target socket that uses the TLM 2.0 generic payload. You can select options for memory mapping, processing times, and input and output buffering. HDL Verifier also generates a SystemC test bench and a report that helps you navigate the generated code.

SystemVerilog DPI Component Generation

HDL Verifier, used with Embedded Coder, lets you export a Simulink subsystem as a Verilog or SystemVerilog component with a Direct Programming Interface (DPI) for behavioral simulation. HDL Verifier creates a test bench to verify the generated component using data from the Simulink model. HDL Verifier also allows you to customize the generated SystemVerilog file, including the ability to tune parameters in the generated SystemVerilog module at simulation time.

The supported HDL Simulators include:

  • Mentor Graphics ModelSim and Questa
  • Cadence Incisive
  • Synopsys® VCS®
SystemVerilog DPI Component Generation
SystemVerilog DPI Component Generation.

Use of HDL Verifier with HDL Coder

HDL Verifier works with HDL Coder to accelerate your FPGA and ASIC design and verification workflow. When you generate HDL code from HDL Coder, you can also generate an HDL cosimulation or FPGA-in-the-loop model.

HDL Verifier lets you integrate automatically generated code with your legacy HDL code using black-box integration. Together with HDL Coder, HDL Verifier completes the workflow for high-integrity applications that adhere to standards such as DO-254.

Using the FPGA-in-the-Loop Wizard to automatically generate an FGPA-in-the-loop model for video sharpening.
Using the FPGA-in-the-Loop Wizard to automatically generate an FPGA-in-the-loop (FIL) model for video sharpening. FIL simulation with HDL Coder lets you efficiently perform design space exploration, accelerate verification of your generated HDL code, and improve hardware implementation.

Supported HDL Simulators and FPGA Boards

HDL Verifier supports HDL simulators including Cadence Incisive, Mentor Graphics ModelSim, and Questa. HDL Verifier also supports FPGA-in-the-loop verification over the Gigabit Ethernet interface for select Xilinx boards and over the Gigabit Ethernet or JTAG interface for select Altera FPGA boards.

To download the support package that enables FPGA-in-the-loop, view examples and videos, and obtain a list of boards supported, see:

For supported HDL simulators, see:

Supported EDA Tools

Try HDL Verifier

Get trial software

Connecting Simulink with your SystemVerilog Workflow for Functional Verification

View webinar