RF Toolbox 2.6

Modeling a High-Speed Backplane (Part 4: Rational Function Model to a Verilog-A Module)

This demo shows how to use RF Toolbox™ functions to generate a Verilog-A module that models the high-level behavior of a high-speed backplane. First, it reads the single-ended 4-port S-parameters for a differential high-speed backplane and converts them to 2-port differential S-parameters. Then, it computes the transfer function of the differential circuit and fits a rational function model to the transfer function. Next, the demo exports a Verilog-A module that describes the model. Finally, it plots the unit step response of the generated Verilog-A module in a third-party circuit simulation tool.

Contents

Use a Rational Model to Describe the High-Level Behavior of a High-Speed Backplane

Read a Touchstone® data file into an RFDATA.DATA object using the object's READ method. The parameters in this data file are the 50-ohm S-parameters of a single-ended 4-port passive circuit, measured at 1496 frequencies ranging from 50 MHz to 15 GHz. Then, extract the single-ended 4-port S-parameters from the RFDATA.DATA object, use the S2SDD function to convert them to differential 2-port S-parameters, and use the S2TF function to compute the transfer function of the differential circuit. Then, use the RATIONALFIT function to generate an RFMODEL.RATIONAL object that describes the high-level behavior of this high-speed backplane. The RFMODEL.RATIONAL object is a rational function model that expresses the circuit's transfer function in closed form using poles, residues, and other parameters, as described in the RATIONALFIT reference page.

FileName = 'default.s4p';
SingleEndedData = read(rfdata.data, FileName);
[SingleEndedSparams, Freq] = extract(SingleEndedData, 'S-Parameters', 50);
DifferentialSparams = s2sdd(SingleEndedSparams);  % Convert to 2-port S-para
meters
DifferentiaTransFunc = s2tf(DifferentialSparams); % Convert to transfer func
tion
FittingTolerance = -30;           % Rational fitting tolerance in dB
Weight = ones(size(Freq));        % Fitting weight
DelayFactor = 0.9;                % Delay factor
RationalModel = rationalfit(Freq, DifferentiaTransFunc, ...
    FittingTolerance, Weight, DelayFactor)

RationalModel =

     Name: 'Rational Function'
        A: [22x1 double]
        C: [22x1 double]
        D: 0
    Delay: 6.0172e-009

Export the Rational Model as a Verilog-A Module

Use the WRITEVA method of the RFMODEL.RATIONAL object to export the rational model as a Verilog-A module, called samplepassive1, that describes the rational model. The input and output nets of samplepassive1 are called line_in and line_out. The predefined Verilog-A discipline, electrical, describes the attributes of these nets. The format of numeric values, such as the Laplace transform numerator and denominator coefficients, is %12.10e. The electrical discipline is defined in the file, disciplines.vams, which is included in the beginning of the samplepassive1.va file.

workingdir = tempname;
mkdir(workingdir)
writeva(RationalModel, fullfile(workingdir,'samplepassive1'), ...
    'line_in', 'line_out', 'electrical', '%12.10e', 'disciplines.vams');

type(fullfile(workingdir,'samplepassive1.va'));

// Module: samplepassive1

// Generated by MATLAB(R) 7.9 and the RF Toolbox 2.6.

// Generated on: 30-Jun-2009 09:37:57

`include "disciplines.vams"

module samplepassive1(line_in, line_out);
 electrical line_in, line_out;
 electrical node1;

 real nn1[0:1], nn2[0:1], nn3[0:1], nn4[0:1], nn5[0:1], nn6[0:1], nn7[0:1], 
nn8[0:1], nn9[0:1], nn10[0:0], nn11[0:1], nn12[0:0];
 real dd1[0:2], dd2[0:2], dd3[0:2], dd4[0:2], dd5[0:2], dd6[0:2], dd7[0:2], 
dd8[0:2], dd9[0:2], dd10[0:1], dd11[0:2], dd12[0:1];

 analog begin

   @(initial_step) begin
     nn1[0] = 5.3239575939e+017;
     nn1[1] = -1.6776943750e+007;
     dd1[0] = 4.6793968641e+021;
     dd1[1] = 2.2330129127e+009;
     dd1[2] = 1.0000000000e+000;
     nn2[0] = 2.1093015382e+018;
     nn2[1] = -7.8972108017e+007;
     dd2[0] = 3.4021324054e+021;
     dd2[1] = 3.9623706928e+009;
     dd2[2] = 1.0000000000e+000;
     nn3[0] = -5.3659518940e+018;
     nn3[1] = -1.9435042778e+008;
     dd3[0] = 2.5731964849e+021;
     dd3[1] = 5.5820738613e+009;
     dd3[2] = 1.0000000000e+000;
     nn4[0] = -1.0796847224e+019;
     nn4[1] = -7.2146367895e+008;
     dd4[0] = 1.5608090425e+021;
     dd4[1] = 6.3998786168e+009;
     dd4[2] = 1.0000000000e+000;
     nn5[0] = -6.2015501533e+019;
     nn5[1] = -4.8814091826e+008;
     dd5[0] = 1.0486441402e+021;
     dd5[1] = 7.0604842610e+009;
     dd5[2] = 1.0000000000e+000;
     nn6[0] = -7.9870455853e+019;
     nn6[1] = 3.3792684987e+009;
     dd6[0] = 5.9842856907e+020;
     dd6[1] = 9.0467314634e+009;
     dd6[2] = 1.0000000000e+000;
     nn7[0] = 8.7274992381e+019;
     nn7[1] = 9.4797137987e+009;
     dd7[0] = 2.9056793936e+020;
     dd7[1] = 8.6670317332e+009;
     dd7[2] = 1.0000000000e+000;
     nn8[0] = 1.1487278516e+020;
     nn8[1] = -1.1082968318e+009;
     dd8[0] = 1.1644911019e+020;
     dd8[1] = 7.7111122316e+009;
     dd8[2] = 1.0000000000e+000;
     nn9[0] = -8.2701418117e+018;
     nn9[1] = 6.1511791648e+008;
     dd9[0] = 4.0356325858e+019;
     dd9[1] = 4.4854498234e+009;
     dd9[2] = 1.0000000000e+000;
     nn10[0] = 7.2854928182e+006;
     dd10[0] = 3.7091494775e+008;
     dd10[1] = 1.0000000000e+000;
     nn11[0] = -3.1573342964e+018;
     nn11[1] = -1.1083900606e+010;
     dd11[0] = 1.5123919365e+019;
     dd11[1] = 7.1482978653e+009;
     dd11[2] = 1.0000000000e+000;
     nn12[0] = 1.3577798660e+008;
     dd12[0] = 6.1421700650e+008;
     dd12[1] = 1.0000000000e+000;
   end

   V(node1) <+ laplace_nd(V(line_in), nn1, dd1);
   V(node1) <+ laplace_nd(V(line_in), nn2, dd2);
   V(node1) <+ laplace_nd(V(line_in), nn3, dd3);
   V(node1) <+ laplace_nd(V(line_in), nn4, dd4);
   V(node1) <+ laplace_nd(V(line_in), nn5, dd5);
   V(node1) <+ laplace_nd(V(line_in), nn6, dd6);
   V(node1) <+ laplace_nd(V(line_in), nn7, dd7);
   V(node1) <+ laplace_nd(V(line_in), nn8, dd8);
   V(node1) <+ laplace_nd(V(line_in), nn9, dd9);
   V(node1) <+ laplace_nd(V(line_in), nn10, dd10);
   V(node1) <+ laplace_nd(V(line_in), nn11, dd11);
   V(node1) <+ laplace_nd(V(line_in), nn12, dd12);
   V(line_out) <+ absdelay(V(node1), 6.0171901584e-009);
 end
endmodule

Plot the Unit Step Response of the Generated Verilog-A Module

Many third-party circuit simulation tools support the Verilog-A standard. These tools simulate standalone components defined by Verilog-A modules and circuits that contain these components. The following figure shows the unit step response of the samplepassive1 module. The figure was generated with a third-party circuit simulation tool.

Figure 1: The unit step response.

delete(fullfile(workingdir,'samplepassive1.va'));
rmdir(workingdir)