Signal Processing Blockset 6.10

GSM Digital Down Converter

This demo simulates steady-state behavior of a fixed-point digital down converter for GSM (Global System for Mobile) baseband conversions. The demo model uses blocks from Simulink® and the Signal Processing Blockset™ to emulate the operation of the TI GC4016 Quad Digital Down Converter.

In this model, the digital down converter (DDC) accepts a high sample-rate bandpass signal, which may be 50 to 100 MSPS or higher.

The DDC performs:

The DDC produces a low sample-rate (270 KSPS) baseband signal, ready for demodulation.

You can modify the parameters of the blocks in the demo model to observe the possibilities for modeling a customized DDC with Simulink.

Contents

Changing the GSM Source

The GSM Source block in the demo model allows you to switch between a chirp and a sinusoid signal. You can replace this block with a different source to model your application, however you will have to adjust the parameters of the NCO block accordingly.

Adjusting NCO Block Parameters

Look at the output of the NCO Cosine Spectrum scope block to observe the effects of tuning NCO block parameters.

Frequency and Phase

Adjusting the 32-bit Tuning Freq Register Value and 16-bit Phase Offset Register Value inputs to the NCO block allows you to ensure that your GSM source signal gets received and mixed down with minimum error.

Since this demo is simulating the TI GC4016 Quad Digital Down Converter, these frequency and phase signals must be entered in a particular format. The 32-bit Tuning Freq Register Value should be an unsigned 32-bit data type with a 32-bit fraction length. It must also be normalized between 0 and 1.

The Phase Offset Register Value should be an unsigned 16-bit data type with a 16-bit fraction length. It must also be normalized between 0 and 1. The range gets mapped to a range of 0 to 2*pi radians by the hardware.

Dithering

In order to spread the spurious frequencies throughout the available bandwidth, we can add a dither signal to the accumulator phase values. In this demo, the dither signal is generated with binary shift registers and exclusive-or gates. The number of dither bits is automatically determined by

number of dither bits = accumulator word length - table address word length

When we increase the number of dither bits beyond the optimal value, the noise floor begins to rise. When we decrease the number of dither bits below the optimal value, the appearance of spurious frequencies will decrease the spurious free dynamic range of the NCO system.

Adjusting Filter Parameters

The CIC Decimator, Compensation FIR, and Programmable FIR blocks are used together to achieve:

You can use Filter Design and Analysis tool (FDATool) to visualize and analyze the filters. Refer to the Signal Processing Toolbox™ documentation to learn about FDATool.

Double-clicking on the CIC Decimator block in the demo model allows you to see the implementation of the filter. To customize the DDC, you can change the CIC filter by editing the CIC Decimation block parameters.

CIC Decimation filters are implemented using integer overflow "wrap" arithmetic in order to properly perform the decimation filtering within their cascaded integrator-comb structures. This type of filter is economical for implementation on hardware such as FPGAs and ASICs, since the only arithmetic operation required is summing; no multiplies are required. For more information on CIC filters please refer to Hogenauer, E. B., "An Economical Class of Digital Filters for Decimation and Interpolation," IEEE® Transactions on Acoustics, Speech, and Signal Processing, ASSP-29(2):155 - 162, 1981.

The Compensation FIR block adjusts for roll-off of the CIC passband, and the Programmable FIR block filters the signal to meet the requirements of the GSM baseband spectral mask. You can adjust the gain and coefficients of these filters.

The input gain to Compensation FIR filter is set through the COARSE gain parameter. The TI GC4016 Quad Digital Down Converter requires input from a COARSE parameter to shift the output of the CIC filter by 0 - 7 bits, according to 2^COARSE.

Thus you may enter 0 - 7 for the COARSE gain parameter in the Coarse Gain block mask.

The gain at the output of the Programmable FIR block is set through the FINE gain parameter. The TI GC4016 Quad Digital Down Converter requires input from a FINE parameter to shift the signal by 1 - 4 bits, according to FINE/1024.

Thus you may enter 1 to 16383 for the FINE gain parameter in the Fine Gain block mask.

Adjusting Rate Conversion Block Parameters

This final stage of the DDC can be used to change the rate of the output of the DDC to match the baseband frequency of your particular system's demodulator input. The Rate Conversion block is a fixed-point filter that acts similarly to the FIR Rate Conversion block in the Signal Processing Blockset™ . The Rate Conversion block's NDELAY parameter is the interpolation factor, and the NDEC parameter is the decimation factor.

Analyzing the DDC

You can use scopes and the Fixed-Point Settings interface to observe and analyze the results of your simulation.

Scopes

Double-click on the Scopes block in the demo model to gain access to the following scopes:

Fixed-Point Settings Interface

Invoke the Fixed-Point Settings interface for the demo by going to the Tools menu and selecting Fixed-Point Settings. This interface allows you to see the maximum values, minimum values, and overflows for fixed-point blocks in any subsystem in the demo model. Refer to the Simulink and Simulink® Fixed Point™ documentation for more information on the Fixed-Point Settings interface.

More Information

More information on the GC4016 device may be obtained from the Texas Instruments™ website http://focus.ti.com/docs/prod/folders/print/gc4016.html.

A full PDF specification is also available from Texas Instruments. http://www-s.ti.com/sc/ds/gc4016.pdf