Simulink Design Optimization

Meeting Requirements Specified by Model Verification Blocks

Simulink Design Optimization supports the optimization of model parameters to meet design requirements specified by Model Verification blocks in Simulink, Simulink Control Design, and Simulink Design Optimization block libraries.

Model Verification blocks enable you to verify that your design meets time-domain and frequency-domain requirements such as time-dependent upper and lower bounds on signal value, frequency-dependent Bode plot magnitude constraints, step response bounds, and gain and phase margins. Model Verification blocks detect requirement violations. You can configure the blocks to stop the simulation when a violation is detected or log the event for further analysis.

You can use Simulink Design Optimization to automatically tune model parameters to ensure that all design requirements specified by Model Verification blocks are met.

Model Verification block libraries in Simulink Design Optimization (top) and Simulink Control Design (bottom).