Simulink Design Verifier

Simulink Design Verifier™ uses formal methods to identify hard–to-find design errors in models without requiring extensive tests or simulation runs. Design errors detected include dead logic, integer overflow, division by zero, and violations of design properties and assertions.

Simulink Design Verifier highlights blocks in the model containing these errors and blocks proven to be without them. For each block with an error, it calculates signal-range boundaries and generates a test vector that reproduces the error in simulation.

The generated test vectors provide simulation inputs that exercise functionality captured in the model structure and specified by the test objectives. The test vectors, together with the design properties and test objectives, can be used to verify code running in software-in-the-loop (SIL) and processor-in-the-loop (PIL) test configurations.

Learn more about verification, validation, and test in Model-Based Design.