Simulink Design Verifier 1.5

Introduction

Simulink Design Verifier generates tests for your Simulink and Stateflow models that satisfy model coverage and user-defined objectives. It also proves model properties and generates examples of violations.

Simulink Design Verifier supports the following model coverage objectives: decision, condition, and modified condition/decision coverage (MC/DC). You can define custom test objectives directly in your Simulink or Stateflow models by using design verification blocks. With property proving, you can explore your design for flaws, missed requirements, and unwanted states, issues that are difficult to uncover by simulation alone.

Key Features

• Generates tests for Simulink and Stateflow models and Embedded MATLAB functions
• Detects unreachable design elements in models
• Proves model properties and generates examples of violations
• Supports fixed-point and floating-point models
• Supports modeling styles that include model reference and nonvirtual buses
• Produces test-generation and property-proving analysis reports

Tests in a model harness and associated report generated by Simulink Design Verifier. These tests can then be run in simulation. Click on image to see enlarged view.