Simulink® Design Verifier™ 1.2

Product Description

• Introduction and Key Features
• Working with Simulink Design Verifier
• Formal Methods with Prover® Plug-In
• Test Generation
• Property Proving
• Extending Design Verifier

Working with Simulink Design Verifier

Simulink Design Verifier integrates with the Simulink and Stateflow design environments. You can launch it from the MATLAB command line or the Simulink tool menu.

With Simulink Design Verifier you can:

• Generate input values and parameters for your models to achieve full model coverage, demonstrate violations of requirements, and drive the model to a desired configuration
• Generate harness models for testing of your component in simulation and further analysis
• Refine input values with Simulink Design Verifier constraint blocks
• Identify unachievable model coverage, such as states that cannot be entered, switch conditions that cannot occur, and subsystems that cannot execute
• Specify functional requirements in your model and verify them using property proving
• Confirm model robustness under extreme conditions
• Produce detailed test-generation and property-proving analysis reports

Simulink Design Verifier supports the discrete-time subset of Simulink and Stateflow typically used in embedded control designs. It includes tools for identifying and refactoring incompatible portions of a model.

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