Simulink Design Verifier
Product Description
- Introduction and Key Features
- Formal Methods in Model-Based Design
- Error Detection Using Formal Methods
- Verification of Designs Against Requirements
- Model Coverage Analysis
Extending Design Verifier
The Verification Subsystem block from the Simulink Design Verifier library lets you define complex proof objectives and constraints using Simulink and Stateflow constructs without affecting the simulation or code generated by Real-Time Workshop. All Simulink Design Verifier functionality can be scripted and then executed in batch mode in MATLAB using command-line functions. Simulink Design Verifier options are saved in your Simulink model files and can be modified using standard Simulink functions.
