Simulink HDL Coder

Introduction

Simulink HDL Coder™ generates bit-true and cycle-accurate, synthesizable Verilog^® and VHDL^® code from Simulink^® models, MATLAB^® code, and Stateflow^® charts. The generated HDL code can be simulated and synthesized using industry-standard tools and then implemented on FPGAs and ASICs.

With Simulink HDL Coder you can control HDL architecture and implementation, highlight critical paths in the model, and generate hardware resource utilization estimates. For rapid verification, Simulink HDL Coder generates test benches and EDA Simulator Link™ cosimulation models, and provides code traceability to support the DO-254 workflow.

Key Features

• Generation of target-independent, synthesizable HDL code from Simulink models, MATLAB code, and Stateflow charts
• Support for Mealy and Moore finite-state machines and control logic implementations
• Generation of test benches and EDA Simulator Link cosimulation models
• Resource sharing and subsystem-level retiming options for area-speed tradeoffs
• Simulink model optimization using timing constraint information and HDL synthesis tools
• Code-to-model and model-to-code traceability for DO-254
• Legacy code integration

Generating HDL code from a Simulink model. Simulink HDL Coder enables you to model your system and then automatically generate bit-true and cycle-accurate synthesizable Verilog and VHDL code and test benches.