Simulink HDL Coder 1.6

Introduction

Simulink HDL Coder generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models, Stateflow charts, and Embedded MATLAB code. The automatically generated HDL code is target independent.

Simulink HDL Coder generates Verilog code that complies with the IEEE 1364-2001 standard and VHDL code that complies with the IEEE 1076 standard. As a result, you can verify the automatically generated HDL code using popular functional verification products, including Cadence® Incisive®, Mentor Graphics® ModelSim®, and Synopsys® VCS®.  You can also map the automatically generated HDL code into field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) using popular synthesis tools, such as Altera® Quartus® II, Cadence Encounter® RTL Compiler, Mentor Graphics® Precision®, Synopsys Design Compiler®, Synplicity® Synplify®, and Xilinx® ISE™.

Simulink HDL Coder also generates HDL test benches that help you verify the generated HDL code using HDL simulation tools.

Key Features

• Generates synthesizable HDL code from Simulink models and Embedded MATLAB™ code for datapath implementations
• Generates synthesizable HDL code from Stateflow charts for Mealy and Moore finite-state machines and control logic implementations
• Generates VHDL code that is IEEE 1076 compliant and Verilog code that is IEEE 1364-2001 compliant
• Lets you create bit-true and cycle-accurate models that match your Simulink design specifications
• Lets you select from multiple HDL architectural implementations for commonly used blocks
• Lets you specify the subsystem for HDL code generation
• Enables you to reuse existing IP HDL code (with EDA Simulator Link products)
• Generates simulation and synthesis scripts

You can use Simulink to model your system and then automatically generate bit-true, cycle-accurate, synthesizable Verilog and VHDL code and test benches. Click on image to see enlarged view.