Simulink HDL Coder 1.6

Working with Simulink HDL Coder

Simulink HDL Coder bridges the gap between system design and hardware implementation. It lets you generate synthesizable, correct-by-construction HDL code that can be used to rapidly design, verify, and develop prototypes of signal processing algorithms. By using Simulink HDL Coder, you can model your system in Simulink, Stateflow, and Embedded MATLAB™ code, and then generate HDL code for the datapath and control sections of your design.

Once you have modeled and simulated your finite-state machines in Stateflow, you can use Simulink HDL Coder to generate synthesizable Verilog and VHDL code. Click on image to see larger view.

Simulink HDL Coder provides multiple options that let you control the type and structure of HDL code. You can use the built-in graphical user interface (GUI) or a code generation control file to make your selections. You can choose the polarity, type, and port name of the reset signal along with language-specific options for Verilog and VHDL. You can also define a default HDL code generation template that can be used across the organization.

You can use a GUI or text code generation control file to set HDL code generation parameters. Click on image to see larger view.

You can use the automatically generated Verilog and VHDL code for rapid proto­typing, formal and functional verification of hand-coded HDL, and other applications. Simulink HDL Coder generates simulation and synthesis scripts that enable you to quickly simulate and synthesize your design.