Simulink HDL Coder

Working with Simulink HDL Coder

Simulink HDL Coder lets you automate your algorithm design process, from modeling to FPGA and ASIC implementation, with these steps:

• Model your system using Simulink, MATLAB code, and Stateflow charts
• Configure parameters to select different HDL block implementations
• Optimize models to meet area-speed design objectives
• Generate HDL code using the HDL Workflow Advisor or the Configuration Parameters GUI
• Verify generated code using test benches and automatically generated cosimulation models

You start the HDL code generation process by first modeling your algorithm in Simulink, MATLAB, or Stateflow. You can select from more than 160 Simulink blocks from add-on products for signal processing and communications to model your algorithm. For example, you can use the Viterbi decoder or Reed-Solomon decoder to model communications receivers and generate HDL code. Similarly, you can use signal processing FFT function and filtering algorithms, including CIC and FIR interpolation and decimation filters.

You can generate HDL code from your MATLAB code by using the MATLAB function block in Simulink. Simulink HDL Coder provides a library of common and ready-to-use logic elements, such as counters and timers that are written in MATLAB code. You can also model your finite-state machine (FSM) in Stateflow and integrate your handwritten or legacy HDL code into the Simulink model via black-box interfaces.

Once you have created your model, you can use the HDL Workflow Advisor or the Configuration Parameters GUI to apply code generation constraints and generate HDL code.

Configuration Parameters GUI for setting code generation options and generating Verilog and VHDL code.

Simulink HDL Coder works with EDA Simulator Link to perform FPGA-in-the-loop (FIL) simulations and HDL cosimulations. In addition, you can generate HDL test benches and script files for standalone verification in your HDL simulation environment.