Simulink HDL Coder
Product Description
- Introduction and Key Features
- Working with Simulink HDL Coder
- Optimizing Design
- Documenting and Tracing Code
- Cosimulation and Test-Bench Generation
- Automating FPGA Design
Optimizing Design
Resource utilization report for performing area-speed tradeoffs.
Simulink HDL Coder lets you control the architecture of the HDL code at a block and subsystem level in your model. For example, you can employ distributed pipelining, streaming, and resource sharing for subsystems, Stateflow charts, and MATLAB function blocks, to achieve speed-area tradeoffs in your FPGA and ASIC implementations. You can also implement multichannel designs and serialization techniques that are commonly used in signal processing and multimedia applications.
Resource-optimization example. Replacing four multipliers with one multiplier reduces the design area at the cost of increasing the data rate by a factor of four.
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