Simulink HDL Coder
Product Description
- Introduction and Key Features
- Working with Simulink HDL Coder
- Optimizing Design
- Documenting and Tracing Code
- Cosimulation and Test-Bench Generation
- Automating FPGA Design
Cosimulation and Test-Bench Generation
Simulink HDL Coder generates VHDL and Verilog test benches to enable rapid verification of the generated HDL code. You can customize an HDL test bench using a variety of options that apply stimuli to the HDL code. You can also generate script files to automate the process of compiling and simulating your code in HDL simulators.
Simulink HDL Coder works with EDA Simulator Link to generate a cosimulation model. The automatically generated model is configured for both Simulink simulation and cosimulation with an HDL simulator, such as Cadence Incisive or Mentor Graphics ModelSim and Questa. You can also use the generated model to perform FPGA-in-the-loop simulations.
Automatic instantiation of cosimulation model (bottom, left) and generation of HDL test bench (top, right) using Simulink HDL Coder.
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