Simulink HDL Coder

Automating FPGA Design

FPGA design workflow with Simulink HDL Coder. The HDL Workflow Advisor works with third-party synthesis tools, such as Xilinx ISE and Altera Quartus II, for rapid design iterations.

Simulink HDL Coder enables you to quickly implement your Simulink model in Xilinx and Altera FPGAs. The HDL Workflow Advisor supports and integrates all stages of the FPGA design process, including:

• Checking the Simulink model for HDL code generation compatibility
• Generating RTL code, an RTL test bench, and a cosimulation model
• Performing synthesis and timing analysis through integration with Xilinx ISE and Altera Quartus II
• Providing a resource estimation report and guidance on modifying the model to achieve design constraints
• Back annotating the Simulink model with critical path information

HDL Workflow Advisor, which supports all stages of the FPGA design process from within Simulink.

You can view a postsynthesis timing report and back annotate the Simulink model to identify timing-constraint bottlenecks. Such integration with synthesis tools provides for rapid design iterations and significantly reduces FPGA design cycle time.

Critical path highlighting of presynthesis and postsynthesis timing information in Simulink. You can quickly iterate on your design to eliminate timing-constraint bottlenecks.

Simulink HDL Coder generates HDL code that is readable, target-independent, and supports legacy code integration. As a result, you can quickly transition between FPGA and ASIC implementations based on your design requirements.