Simulink HDL Coder
Generate HDL code from Simulink models and MATLAB code
Product Overview 2:19
Simulink HDL Coder™ generates bit-true and cycle-accurate, synthesizable Verilog® and VHDL® code from Simulink® models, MATLAB® code, and Stateflow® charts. The generated HDL code can be simulated and synthesized using industry-standard tools and then implemented on FPGAs and ASICs.
With Simulink HDL Coder you can control HDL architecture and implementation, highlight critical paths in the model, and generate hardware resource utilization estimates. For rapid verification, Simulink HDL Coder generates test benches and EDA Simulator Link™ cosimulation models, and provides code traceability to support the DO-254 workflow.
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Free ASIC
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The Simulink environment is ideal for system-level architecture exploration. The simulations are 200 times faster than they were in our previous workflow—and Simulink models can be easily converted to C as well as to HDL code, which enables high scalability and reusability.
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